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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Atmel SAM3 clock setup.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "clock_sam3.h"
39 #include <cfg/compiler.h>
40 #include <cfg/macros.h>
44 /* Frequency of board main oscillator */
45 // TODO: wizard config
46 #define BOARDOSC_FREQ 12000000
48 /* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
49 #define BOARD_OSC_COUNT (CKGR_MOR_MOSCXTST(0x8))
51 /* Timer countdown timeout for clock initialization operations */
52 #define CLOCK_TIMEOUT 0xFFFFFFFF
56 * Try to evaluate the correct divider and multiplier value depending
57 * on the desired CPU frequency.
59 * We try all combinations in a certain range of divider and multiplier
60 * values. The range can change, with better match with "strange"
61 * frequencies, but boot time will be longer.
63 * Limits for SAM3N: divider [1,255], multiplier [1,2047].
65 INLINE uint32_t evaluate_pll(void)
67 int mul, div, best_mul, best_div;
68 int best_delta = CPU_FREQ;
71 for (mul = 1; mul <= 8; mul++)
73 for (div = 1; div <= 24; div++)
75 freq = BOARDOSC_FREQ / div * (1 + mul);
76 if (ABS((int)CPU_FREQ - freq) < best_delta) {
77 best_delta = ABS((int)CPU_FREQ - freq);
84 return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul);
92 /* Disable watchdog */
93 WDT_MR = BV(WDT_WDDIS);
96 /* Set wait states for flash access, needed for higher CPU clock rates */
97 EEFC0_FMR = EEFC_FMR_FWS(2);
98 EEFC1_FMR = EEFC_FMR_FWS(2);
100 EEFC0_FMR = EEFC_FMR_FWS(3);
102 // TODO: check if this is needed in sam3n-ek too, very slow start-up
103 // Select external slow clock
104 if (!(SUPC_SR & BV(SUPC_SR_OSCSEL)))
106 SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5);
107 while (!(SUPC_SR & BV(SUPC_SR_OSCSEL)));
111 // Initialize main oscillator
112 if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
114 CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
115 timeout = CLOCK_TIMEOUT;
116 while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
119 // Switch to external oscillator
120 CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
121 timeout = CLOCK_TIMEOUT;
122 while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout);
124 PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK;
125 timeout = CLOCK_TIMEOUT;
126 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
128 // Initialize and enable PLL clock
129 CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1);
130 timeout = CLOCK_TIMEOUT;
131 while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
133 PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
134 timeout = CLOCK_TIMEOUT;
135 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
137 PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
138 timeout = CLOCK_TIMEOUT;
139 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
141 /* Enable clock on PIO for inputs */
142 // TODO: move this in gpio_init() for better power management?
144 PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID)
145 | BV(PIOD_ID) | BV(PIOE_ID) | BV(PIOF_ID);
147 PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID);