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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief ATSAM3 clock setup.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "clock_sam3.h"
39 #include <io/sam3_pmc.h>
40 #include <io/sam3_sysctl.h>
41 #include <io/sam3_flash.h>
42 #include <cfg/compiler.h>
43 #include <cfg/macros.h>
46 /* Frequency of board main oscillator */
47 #define BOARDOSC_FREQ 12000000
49 /* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
50 #define BOARD_OSC_COUNT (CKGR_MOR_MOSCXTST(0x8))
52 /* Timer countdown timeout for clock initialization operations */
53 #define CLOCK_TIMEOUT 0xFFFFFFFF
57 * Try to evaluate the correct divider and multiplier value depending
58 * on the desired CPU frequency.
60 * We try all combinations in a certain range of divider and multiplier
61 * values. The range can change, with better match with "strange"
62 * frequencies, but boot time will be longer.
64 * Limits for SAM3N: divider [1,255], multiplier [1,2047].
66 INLINE uint32_t evaluate_pll(void)
68 int mul, div, best_mul, best_div;
69 int best_delta = CPU_FREQ;
72 for (mul = 1; mul <= 8; mul++)
74 for (div = 1; div <= 24; div++)
76 freq = BOARDOSC_FREQ / div * (1 + mul);
77 if (ABS((int)CPU_FREQ - freq) < best_delta) {
78 best_delta = ABS((int)CPU_FREQ - freq);
85 // Bit 29 must always be set to 1
86 return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
94 /* Set 4 wait states for flash access, needed for higher CPU clock rates */
95 EEFC_FMR = EEFC_FMR_FWS(3);
97 // Select external slow clock
98 if (!(SUPC_SR_R & SUPC_SR_OSCSEL))
100 SUPC_CR_R = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
101 while (!(SUPC_SR_R & SUPC_SR_OSCSEL));
104 // Initialize main oscillator
105 if (!(CKGR_MOR_R & CKGR_MOR_MOSCSEL))
107 CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
108 timeout = CLOCK_TIMEOUT;
109 while (!(PMC_SR_R & PMC_SR_MOSCXTS) && --timeout);
112 // Switch to external oscillator
113 CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
114 timeout = CLOCK_TIMEOUT;
115 while (!(PMC_SR_R & PMC_SR_MOSCSELS) && --timeout);
117 PMC_MCKR_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M) | PMC_MCKR_CSS_MAIN_CLK;
118 timeout = CLOCK_TIMEOUT;
119 while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
121 // Initialize and enable PLL clock
122 CKGR_PLLR_R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
123 timeout = CLOCK_TIMEOUT;
124 while (!(PMC_SR_R & PMC_SR_LOCK) && --timeout);
126 PMC_MCKR_R = PMC_MCKR_CSS_MAIN_CLK;
127 timeout = CLOCK_TIMEOUT;
128 while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
130 PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
131 timeout = CLOCK_TIMEOUT;
132 while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);