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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief AT91SAM3 clocking driver.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "clock_sam3.h"
39 #include <io/sam3_pmc.h>
40 #include <cfg/compiler.h>
41 #include <cfg/macros.h>
43 /* Value to use when writing CKGR_MOR, to unlock write */
47 * Try to evaluate the correct divider and multiplier value depending
48 * on the desired CPU frequency.
50 * We try all combinations in a certain range of divider and multiplier
51 * values. The range can change, with better match with "strange"
52 * frequencies, but boot time will be longer.
54 * Limits for SAM3N: divider [1,255], multiplier [1,2047].
56 INLINE uint32_t evaluate_pll(void)
58 int mul, div, best_mul, best_div;
59 int best_delta = CPU_FREQ;
62 for (mul = 1; mul <= 8; mul++)
64 for (div = 1; div <= 24; div++)
66 // RC oscillator set to 12 MHz
67 freq = 12000000 / div * (1 + mul);
68 if (ABS(CPU_FREQ - freq) < best_delta) {
69 best_delta = ABS(CPU_FREQ - freq);
76 // Bit 29 must always be set to 1
77 return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
83 /* Enable and configure internal Fast RC oscillator */
85 CKGR_MOR_KEY(CKGR_KEY) // Unlock key
86 | CKGR_MOR_MOSCRCEN // Main On-Chip RC oscillator enable
87 | CKGR_MOR_MOSCRCF_12MHZ; // RC oscillator frequency
89 /* Master clock: select PLL clock and no prescaling */
90 PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
92 CKGR_PLLR_R = evaluate_pll();