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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Atmel SAM3 clock setup.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "clock_sam3.h"
39 #include <cfg/compiler.h>
40 #include <cfg/macros.h>
44 /* Frequency of board main oscillator */
45 #define BOARDOSC_FREQ 12000000
47 /* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
48 #define BOARD_OSC_COUNT (CKGR_MOR_MOSCXTST(0x8))
50 /* Timer countdown timeout for clock initialization operations */
51 #define CLOCK_TIMEOUT 0xFFFFFFFF
55 * Try to evaluate the correct divider and multiplier value depending
56 * on the desired CPU frequency.
58 * We try all combinations in a certain range of divider and multiplier
59 * values. The range can change, with better match with "strange"
60 * frequencies, but boot time will be longer.
62 * Limits for SAM3N: divider [1,255], multiplier [1,2047].
64 INLINE uint32_t evaluate_pll(void)
66 int mul, div, best_mul, best_div;
67 int best_delta = CPU_FREQ;
70 for (mul = 1; mul <= 8; mul++)
72 for (div = 1; div <= 24; div++)
74 freq = BOARDOSC_FREQ / div * (1 + mul);
75 if (ABS((int)CPU_FREQ - freq) < best_delta) {
76 best_delta = ABS((int)CPU_FREQ - freq);
83 // Bit 29 must always be set to 1
84 return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
92 /* Disable watchdog */
93 WDT_MR = BV(WDT_WDDIS);
95 /* Set 4 wait states for flash access, needed for higher CPU clock rates */
96 EEFC_FMR = EEFC_FMR_FWS(3);
98 // Select external slow clock
99 if (!(SUPC_SR & BV(SUPC_SR_OSCSEL)))
101 SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5);
102 while (!(SUPC_SR & BV(SUPC_SR_OSCSEL)));
105 // Initialize main oscillator
106 if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
108 CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
109 timeout = CLOCK_TIMEOUT;
110 while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
113 // Switch to external oscillator
114 CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
115 timeout = CLOCK_TIMEOUT;
116 while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout);
118 PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK;
119 timeout = CLOCK_TIMEOUT;
120 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
122 // Initialize and enable PLL clock
123 CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1);
124 timeout = CLOCK_TIMEOUT;
125 while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
127 PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
128 timeout = CLOCK_TIMEOUT;
129 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
131 PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
132 timeout = CLOCK_TIMEOUT;
133 while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
135 /* Enable clock on PIO for inputs */
136 PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID);