4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Low-level clocking driver for Cortex-M3 STM32.
35 * \author Andrea Righi <arighi@develer.com>
41 /* RCC registers bit address */
42 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
48 /* Alias word address of HSION bit */
49 #define CR_OFFSET (RCC_OFFSET + 0x00)
50 #define HSION_BITNUMBER 0x00
51 #define CR_HSION_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BITNUMBER * 4)))
53 /* Alias word address of PLLON bit */
54 #define PLLON_BITNUMBER 0x18
55 #define CR_PLLON_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BITNUMBER * 4)))
57 /* Alias word address of CSSON bit */
58 #define CSSON_BITNUMBER 0x13
59 #define CR_CSSON_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BITNUMBER * 4)))
66 /* Alias word address of USBPRE bit */
67 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
68 #define USBPRE_BITNUMBER 0x16
69 #define CFGR_USBPRE_BB ((reg32_t *)(PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BITNUMBER * 4)))
76 /* Alias word address of RTCEN bit */
77 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
78 #define RTCEN_BITNUMBER 0x0F
79 #define BDCR_RTCEN_BB ((reg32_t *)(PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BITNUMBER * 4)))
81 /* Alias word address of BDRST bit */
82 #define BDRST_BITNUMBER 0x10
83 #define BDCR_BDRST_BB ((reg32_t *)(PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BITNUMBER * 4)))
90 /* Alias word address of LSION bit */
91 #define CSR_OFFSET (RCC_OFFSET + 0x24)
92 #define LSION_BITNUMBER 0x00
93 #define CSR_LSION_BB ((reg32_t *)(PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BITNUMBER * 4)))
97 * RCC registers bit mask
100 /* CR register bit mask */
101 #define CR_HSEBYP_RESET (0xFFFBFFFF)
102 #define CR_HSEBYP_SET (0x00040000)
103 #define CR_HSEON_RESET (0xFFFEFFFF)
104 #define CR_HSEON_SET (0x00010000)
105 #define CR_HSITRIM_MASK (0xFFFFFF07)
107 /* CFGR register bit mask */
108 #define CFGR_PLL_MASK (0xFFC0FFFF)
109 #define CFGR_PLLMull_MASK (0x003C0000)
110 #define CFGR_PLLSRC_MASK (0x00010000)
111 #define CFGR_PLLXTPRE_MASK (0x00020000)
112 #define CFGR_SWS_MASK (0x0000000C)
113 #define CFGR_SW_MASK (0xFFFFFFFC)
114 #define CFGR_HPRE_RESET_MASK (0xFFFFFF0F)
115 #define CFGR_HPRE_SET_MASK (0x000000F0)
116 #define CFGR_PPRE1_RESET_MASK (0xFFFFF8FF)
117 #define CFGR_PPRE1_SET_MASK (0x00000700)
118 #define CFGR_PPRE2_RESET_MASK (0xFFFFC7FF)
119 #define CFGR_PPRE2_SET_MASK (0x00003800)
120 #define CFGR_ADCPRE_RESET_MASK (0xFFFF3FFF)
121 #define CFGR_ADCPRE_SET_MASK (0x0000C000)
123 /* CSR register bit mask */
124 #define CSR_RVMF_SET (0x01000000)
127 #define FLAG_MASK (0x1F)
129 /* Typical VALUE of the HSI in Hz */
130 #define HSI_VALUE (8000000)
132 /* BDCR register base address */
133 #define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET)
136 #define RCC_FLAG_HSIRDY (0x20)
137 #define RCC_FLAG_HSERDY (0x31)
138 #define RCC_FLAG_PLLRDY (0x39)
139 #define RCC_FLAG_LSERDY (0x41)
140 #define RCC_FLAG_LSIRDY (0x61)
141 #define RCC_FLAG_PINRST (0x7A)
142 #define RCC_FLAG_PORRST (0x7B)
143 #define RCC_FLAG_SFTRST (0x7C)
144 #define RCC_FLAG_IWDGRST (0x7D)
145 #define RCC_FLAG_WWDGRST (0x7E)
146 #define RCC_FLAG_LPWRRST (0x7F)
148 /* System clock source */
149 #define RCC_SYSCLK_HSI (0x00000000)
150 #define RCC_SYSCLK_HSE (0x00000001)
151 #define RCC_SYSCLK_PLLCLK (0x00000002)
153 /* PLL entry clock source */
154 #define RCC_PLL_HSI_DIV2 (0x00000000)
155 #define RCC_PLL_HSE_DIV1 (0x00010000)
156 #define RCC_PLL_HSE_DIV2 (0x00030000)
158 /* PLL multiplication factor */
159 #define RCC_PLLMUL_2 (0x00000000)
160 #define RCC_PLLMUL_3 (0x00040000)
161 #define RCC_PLLMUL_4 (0x00080000)
162 #define RCC_PLLMUL_5 (0x000C0000)
163 #define RCC_PLLMUL_6 (0x00100000)
164 #define RCC_PLLMUL_7 (0x00140000)
165 #define RCC_PLLMUL_8 (0x00180000)
166 #define RCC_PLLMUL_9 (0x001C0000)
167 #define RCC_PLLMUL_10 (0x00200000)
168 #define RCC_PLLMUL_11 (0x00240000)
169 #define RCC_PLLMUL_12 (0x00280000)
170 #define RCC_PLLMUL_13 (0x002C0000)
171 #define RCC_PLLMUL_14 (0x00300000)
172 #define RCC_PLLMUL_15 (0x00340000)
173 #define RCC_PLLMUL_16 (0x00380000)
177 * RCC register: APB1 peripheral
180 #define RCC_APB1_TIM2 (0x00000001)
181 #define RCC_APB1_TIM3 (0x00000002)
182 #define RCC_APB1_TIM4 (0x00000004)
183 #define RCC_APB1_WWDG (0x00000800)
184 #define RCC_APB1_SPI2 (0x00004000)
185 #define RCC_APB1_USART2 (0x00020000)
186 #define RCC_APB1_USART3 (0x00040000)
187 #define RCC_APB1_I2C1 (0x00200000)
188 #define RCC_APB1_I2C2 (0x00400000)
189 #define RCC_APB1_USB (0x00800000)
190 #define RCC_APB1_CAN (0x02000000)
191 #define RCC_APB1_BKP (0x08000000)
192 #define RCC_APB1_PWR (0x10000000)
193 #define RCC_APB1_ALL (0x1AE64807)
197 * RCC register: APB2 peripheral
200 #define RCC_APB2_AFIO (0x00000001)
201 #define RCC_APB2_GPIOA (0x00000004)
202 #define RCC_APB2_GPIOB (0x00000008)
203 #define RCC_APB2_GPIOC (0x00000010)
204 #define RCC_APB2_GPIOD (0x00000020)
205 #define RCC_APB2_GPIOE (0x00000040)
206 #define RCC_APB2_ADC1 (0x00000200)
207 #define RCC_APB2_ADC2 (0x00000400)
208 #define RCC_APB2_TIM1 (0x00000800)
209 #define RCC_APB2_SPI1 (0x00001000)
210 #define RCC_APB2_USART1 (0x00004000)
211 #define RCC_APB2_ALL (0x00005E7D)
214 /* Crystal frequency of the main oscillator (8MHz) */
215 #define PLL_VCO 8000000
217 /* Reset and Clock Controller registers */
232 /* RCC registers base */
233 extern struct RCC *RCC;
235 void clock_init(void);
237 #endif /* CLOCK_STM32_h */