4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief DAC hardware-specific implementation
35 * \author Daniele Basile <asterix@develer.com>
40 #include "cfg/cfg_dac.h"
42 #include <cfg/macros.h>
43 #include <cfg/compiler.h>
45 // Define log settings for cfg/log.h.
46 #define LOG_LEVEL DAC_LOG_LEVEL
47 #define LOG_FORMAT DAC_LOG_FORMAT
51 #include <drv/irq_cm3.h>
63 struct DacHardware dac_hw;
65 #if CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH0 /* Select Timer counter TIO Channel 0 */
66 #define DAC_TC_ID TC0_ID
67 #define DAC_TC_CCR TC0_CCR0
68 #define DAC_TC_IDR TC0_IDR0
69 #define DAC_TC_CMR TC0_CMR0
70 #define DAC_TC_SR TC0_SR0
71 #define DAC_TC_RA TC0_RA0
72 #define DAC_TC_RC TC0_RC0
73 #elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH1 /* Select Timer counter TIO Channel 1 */
74 #define DAC_TC_ID TC1_ID
75 #define DAC_TC_CCR TC0_CCR1
76 #define DAC_TC_IDR TC0_IDR1
77 #define DAC_TC_CMR TC0_CMR1
78 #define DAC_TC_SR TC0_SR1
79 #define DAC_TC_RA TC0_RA1
80 #define DAC_TC_RC TC0_RC1
81 #elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH2 /* Select Timer counter TIO Channel 2 */
82 #define DAC_TC_ID TC2_ID
83 #define DAC_TC_CCR TC0_CCR2
84 #define DAC_TC_IDR TC0_IDR2
85 #define DAC_TC_CMR TC0_CMR2
86 #define DAC_TC_SR TC0_SR2
87 #define DAC_TC_RA TC0_RA2
88 #define DAC_TC_RC TC0_RC2
89 #elif CONFIG_DAC_TIMER == DACC_TRGSEL_PWM0 || CONFIG_DAC_TIMER == DACC_TRGSEL_PWM1
90 #error unimplemented pwm triger select.
93 INLINE void tc_setup(uint32_t freq)
95 pmc_periphEnable(DAC_TC_ID);
97 /* Disable TC clock */
98 DAC_TC_CCR = TC_CCR_CLKDIS;
99 /* Disable interrupts */
100 DAC_TC_IDR = 0xFFFFFFFF;
101 /* Clear status register */
102 volatile uint32_t dummy = DAC_TC_SR;
106 * Setup the timer counter:
107 * - select clock TCLK1
108 * - enable wave form mode
109 * - RA compare effect SET
110 * - RC compare effect CLEAR
111 * - UP mode with automatic trigger on RC Compare
113 DAC_TC_CMR = BV(TC_TIMER_CLOCK1) | BV(TC_CMR_WAVE) | TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR | BV(TC_CMR_CPCTRG);
115 /* Compute the sample frequency */
116 uint32_t rc = (CPU_FREQ / 8) / (freq * 1000);
118 DAC_TC_RA = 50 * rc / 100;
121 INLINE void tc_start(void)
123 DAC_TC_CCR = BV(TC_CCR_CLKEN)| BV(TC_CCR_SWTRG);
126 INLINE void tc_stop(void)
128 DAC_TC_CCR = BV(TC_CCR_CLKDIS);
131 static int sam3x_dac_write(struct Dac *dac, unsigned channel, uint16_t sample)
135 ASSERT(channel <= DAC_MAXCH);
137 DACC_MR |= (channel << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
138 DACC_CHER |= BV(channel);
145 static void sam3x_dac_setCh(struct Dac *dac, uint32_t mask)
147 /* we have only the ch0 and ch1 */
148 ASSERT(mask < BV(3));
149 dac->hw->channels = mask;
152 static void sam3x_dac_setSampleRate(struct Dac *dac, uint32_t rate)
156 /* Eneble hw trigger */
157 DACC_MR |= BV(DACC_TRGEN) | (CONFIG_DAC_TIMER << DACC_TRGSEL_SHIFT);
158 kprintf("%08lx\n", DACC_MR);
162 static void sam3x_dac_conversion(struct Dac *dac, void *buf, size_t len)
164 if (dac->hw->channels & BV(DACC_CH0))
165 DACC_MR |= (DACC_CH0 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
167 if (dac->hw->channels & BV(DACC_CH1))
168 DACC_MR |= (DACC_CH1 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
170 DACC_CHER |= dac->hw->channels;
172 /* Start syncro timer for the dac */
175 /* Setup dma and start it */
176 DACC_TPR = (uint32_t)buf ;
178 DACC_PTCR |= BV(DACC_PTCR_TXTEN);
181 static bool sam3x_dac_isFinished(struct Dac *dac)
186 static void sam3x_dac_start(struct Dac *dac, void *buf, size_t len, size_t slicelen)
190 static void sam3x_dac_stop(struct Dac *dac)
195 void dac_init(struct Dac *dac)
198 /* Fill the virtual table */
199 dac->ctx.write = sam3x_dac_write;
200 dac->ctx.setCh = sam3x_dac_setCh;
201 dac->ctx.setSampleRate = sam3x_dac_setSampleRate;
202 dac->ctx.conversion = sam3x_dac_conversion;
203 dac->ctx.isFinished = sam3x_dac_isFinished;
204 dac->ctx.start = sam3x_dac_start;
205 dac->ctx.stop = sam3x_dac_stop;
206 dac->ctx._type = DAC_SAM3X;
209 /* Clock DAC peripheral */
210 pmc_periphEnable(DACC_ID);
213 DACC_CR |= BV(DACC_SWRST);
216 /* Configure the dac */
217 DACC_MR |= (CONFIG_DAC_REFRESH << DACC_REFRESH_SHIFT) & DACC_REFRESH_MASK;
218 DACC_MR |= (CONFIG_DAC_STARTUP << DACC_STARTUP_SHIFT) & DACC_STARTUP_MASK;