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33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
40 #include "cfg/cfg_eth.h"
42 #define LOG_LEVEL ETH_LOG_LEVEL
43 #define LOG_FORMAT ETH_LOG_FORMAT
47 #include <cfg/debug.h>
49 #include <cfg/macros.h>
50 #include <cfg/compiler.h>
52 // TODO: unify includes
53 //#include <io/at91sam7.h>
55 //#include <io/include.h>
57 #include <drv/irq_cm3.h>
59 #include <cpu/power.h>
60 #include <cpu/types.h>
63 #include <drv/timer.h>
66 #include <mware/event.h>
72 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
73 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
76 * MAC address configuration (please change this in your project!).
78 * TODO: make this paramater user-configurable from the Wizard.
80 const uint8_t mac_addr[] = { 0x00, 0x23, 0x54, 0x6a, 0x77, 0x55 };
82 /* Silent Doxygen bug... */
85 * NOTE: this buffer should be declared as 'volatile' because it is read by the
86 * hardware. However, this is accessed only via memcpy() that should guarantee
87 * coherency when copying from/to buffers.
89 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
90 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
93 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
94 * the hardware. However, this is accessed only via memcpy() that should
95 * guarantee coherency when copying from/to buffers.
97 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
98 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
101 static int tx_buf_idx;
102 static int tx_buf_offset;
103 static int rx_buf_idx;
105 static Event recv_wait, send_wait;
107 static DECLARE_ISR(emac_irqHandler)
109 /* Read interrupt status and disable interrupts. */
110 uint32_t isr = EMAC_ISR;
112 kprintf("irq: %x\n", isr);
114 /* Receiver interrupt */
115 if ((isr & EMAC_RX_INTS))
117 kprintf("emac: rx %x\n", isr);
118 if (isr & BV(EMAC_RCOMP))
119 event_do(&recv_wait);
120 EMAC_RSR = EMAC_RX_INTS;
122 /* Transmitter interrupt */
123 if (isr & EMAC_TX_INTS)
125 if (isr & BV(EMAC_TCOMP))
127 kprintf("emac: tcomp\n");
128 event_do(&send_wait);
130 if (isr & BV(EMAC_RLEX))
131 kprintf("emac: rlex\n");
132 EMAC_TSR = EMAC_TX_INTS;
138 * \brief Read contents of PHY register.
140 * \param reg PHY register number.
142 * \return Contents of the specified register.
144 static uint16_t phy_hw_read(reg8_t reg)
147 EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
148 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE;
150 // Wait until PHY logic completed.
151 while (!(EMAC_NSR & BV(EMAC_IDLE)))
154 // Get data from PHY maintenance register.
155 return (uint16_t)(EMAC_MAN & EMAC_DATA);
159 * \brief Write value to PHY register.
161 * \param reg PHY register number.
162 * \param val Value to write.
164 static void phy_hw_write(reg8_t reg, uint16_t val)
166 // PHY write command.
167 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
168 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE | val;
170 // Wait until PHY logic completed.
171 while (!(EMAC_NSR & BV(EMAC_IDLE)))
175 static int emac_reset(void)
180 //PMC_PCER = BV(PIOA_ID);
181 //PMC_PCER = BV(PIOB_ID);
182 //PMC_PCER = BV(EMAC_ID);
183 // TOOD: Implement in sam7x
184 pmc_periphEnable(PIOA_ID);
185 pmc_periphEnable(PIOB_ID);
186 pmc_periphEnable(EMAC_ID);
189 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
192 PIOB_PUDR = BV(PHY_COL_RMII_BIT);
194 // Disable PHY power down.
195 PIOB_PER = BV(PHY_PWRDN_BIT);
196 PIOB_OER = BV(PHY_PWRDN_BIT);
197 PIOB_CODR = BV(PHY_PWRDN_BIT);
200 // Toggle external hardware reset pin.
201 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
202 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
204 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
207 // Configure MII ports.
209 PIOB_ASR = PHY_MII_PINS;
211 PIOB_PDR = PHY_MII_PINS;
212 // Enable receive and transmit clocks.
213 EMAC_USRIO = BV(EMAC_CLKEN);
215 PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS, PIO_PERIPH_A);
216 PIOB_PDR = PHY_MII_PINS;
217 // Enable receive, transmit clocks and RMII mode.
218 EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
221 // Enable management port.
222 EMAC_NCR |= BV(EMAC_MPE);
223 EMAC_NCFGR |= EMAC_CLK_HCLK_32;
225 // Set local MAC address.
226 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
227 (mac_addr[1] << 8) | mac_addr[0];
228 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
230 // Wait for PHY ready
233 // Clear MII isolate.
234 phy_hw_read(NIC_PHY_BMCR);
235 phy_cr = phy_hw_read(NIC_PHY_BMCR);
237 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
238 phy_hw_write(NIC_PHY_BMCR, phy_cr);
240 phy_cr = phy_hw_read(NIC_PHY_BMCR);
242 LOG_INFO("%s: PHY ID %#04x %#04x\n",
244 phy_hw_read(NIC_PHY_ID1), phy_hw_read(NIC_PHY_ID2));
246 // Wait for auto negotiation completed.
247 phy_hw_read(NIC_PHY_BMSR);
250 if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
255 // Disable management port.
256 EMAC_NCR &= ~BV(EMAC_MPE);
261 static int emac_start(void)
266 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
268 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
269 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
271 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
273 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
275 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
276 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
277 tx_buf_tab[i].stat = TXS_USED;
279 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
281 /* Tell the EMAC where to find the descriptors. */
282 EMAC_RBQP = (uint32_t)rx_buf_tab;
283 EMAC_TBQP = (uint32_t)tx_buf_tab;
285 /* Clear receiver status. */
286 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
288 /* Copy all frames and discard FCS. */
289 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
291 /* Enable receiver, transmitter and statistics. */
292 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
297 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
303 ASSERT(len <= sizeof(tx_buf));
305 /* Check if the transmit buffer is available */
306 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
307 event_wait(&send_wait);
309 /* Copy the data into the buffer and prepare descriptor */
310 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
311 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
313 tx_buf_offset += wr_len;
318 void eth_sendFrame(void)
320 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
322 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
323 EMAC_NCR |= BV(EMAC_TSTART);
326 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
330 ssize_t eth_send(const uint8_t *buf, size_t len)
335 len = eth_putFrame(buf, len);
341 static void eth_buf_realign(int idx)
343 /* Empty buffer found. Realign. */
345 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
346 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
348 } while (idx != rx_buf_idx);
351 static size_t __eth_getFrameLen(void)
353 int idx, n = EMAC_RX_BUFFERS;
356 /* Skip empty buffers */
357 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
359 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
365 LOG_INFO("no frame found\n");
368 /* Search the start of frame and cleanup fragments */
369 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
370 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
372 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
373 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
379 LOG_INFO("no SOF found\n");
382 /* Search end of frame to evaluate the total frame size */
387 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
389 /* Empty buffer found. Realign. */
390 eth_buf_realign(idx);
393 if (rx_buf_tab[idx].stat & RXS_EOF)
394 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
395 if (UNLIKELY((idx != rx_buf_idx) &&
396 (rx_buf_tab[idx].stat & RXS_SOF)))
398 /* Another start of frame found. Realign. */
399 eth_buf_realign(idx);
402 if (++idx >= EMAC_RX_BUFFERS)
406 LOG_INFO("no EOF found\n");
410 size_t eth_getFrameLen(void)
414 /* Check if there is at least one available frame in the buffer */
417 len = __eth_getFrameLen();
420 /* Wait for RX interrupt */
421 event_wait(&recv_wait);
426 ssize_t eth_getFrame(uint8_t *buf, size_t len)
433 ASSERT(len <= sizeof(rx_buf));
435 /* Copy data from the RX buffer */
436 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
437 if (addr + len > &rx_buf[countof(rx_buf)])
439 size_t count = &rx_buf[countof(rx_buf)] - addr;
441 memcpy(buf, addr, count);
442 memcpy(buf + count, rx_buf, len - count);
446 memcpy(buf, addr, len);
448 /* Update descriptors */
451 if (len - rd_len >= EMAC_RX_BUFSIZ)
452 rd_len += EMAC_RX_BUFSIZ;
454 rd_len += len - rd_len;
455 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
457 LOG_INFO("bad frame found\n");
460 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
461 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
468 ssize_t eth_recv(uint8_t *buf, size_t len)
472 len = MIN(len, eth_getFrameLen());
473 return len ? eth_getFrame(buf, len) : 0;
483 event_initGeneric(&recv_wait);
484 event_initGeneric(&send_wait);
486 // Register interrupt vector
487 IRQ_SAVE_DISABLE(flags);
489 /* Disable all emac interrupts */
490 EMAC_IDR = 0xFFFFFFFF;
493 // TODO: define sysirq_set...
494 /* Set the vector. */
495 AIC_SVR(EMAC_ID) = emac_irqHandler;
496 /* Initialize to edge triggered with defined priority. */
497 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
498 /* Clear pending interrupt */
499 AIC_ICCR = BV(EMAC_ID);
500 /* Enable the system IRQ */
501 AIC_IECR = BV(EMAC_ID);
503 sysirq_setHandler(INT_EMAC, emac_irqHandler);
506 /* Enable interrupts */
507 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;