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33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
41 #include "cfg/cfg_eth.h"
43 #define LOG_LEVEL ETH_LOG_LEVEL
44 #define LOG_FORMAT ETH_LOG_FORMAT
48 #include <cfg/debug.h>
50 #include <cfg/macros.h>
51 #include <cfg/compiler.h>
55 #include <drv/irq_cm3.h>
56 #include <drv/timer.h>
59 #include <cpu/power.h>
60 #include <cpu/types.h>
63 #include <mware/event.h>
67 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
68 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
70 /* Silent Doxygen bug... */
73 * NOTE: this buffer should be declared as 'volatile' because it is read by the
74 * hardware. However, this is accessed only via memcpy() that should guarantee
75 * coherency when copying from/to buffers.
77 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
78 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
81 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
82 * the hardware. However, this is accessed only via memcpy() that should
83 * guarantee coherency when copying from/to buffers.
85 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
86 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
89 static int tx_buf_idx;
90 static int tx_buf_offset;
91 static int rx_buf_idx;
93 static Event recv_wait, send_wait;
95 static DECLARE_ISR(emac_irqHandler)
97 /* Read interrupt status and disable interrupts. */
98 uint32_t isr = EMAC_ISR;
100 /* Receiver interrupt */
101 if ((isr & EMAC_RX_INTS))
103 if (isr & BV(EMAC_RCOMP))
104 event_do(&recv_wait);
105 EMAC_RSR = EMAC_RX_INTS;
107 /* Transmitter interrupt */
108 if (isr & EMAC_TX_INTS)
110 if (isr & BV(EMAC_TCOMP))
111 event_do(&send_wait);
112 EMAC_TSR = EMAC_TX_INTS;
118 * \brief Read contents of PHY register.
120 * \param reg PHY register number.
122 * \return Contents of the specified register.
124 static uint16_t phy_hw_read(uint8_t phy_addr, reg8_t reg)
127 EMAC_MAN = EMAC_SOF | EMAC_RW_READ
128 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
129 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
132 // Wait until PHY logic completed.
133 while (!(EMAC_NSR & BV(EMAC_IDLE)))
136 // Get data from PHY maintenance register.
137 return (uint16_t)(EMAC_MAN & EMAC_DATA);
142 * \brief Write value to PHY register.
144 * \param reg PHY register number.
145 * \param val Value to write.
147 static void phy_hw_write(uint8_t phy_addr, reg8_t reg, uint16_t val)
149 // PHY write command.
150 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE
151 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
152 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
155 // Wait until PHY logic completed.
156 while (!(EMAC_NSR & BV(EMAC_IDLE)))
162 * Check link speed and duplex as negotiated by the PHY
163 * and configure CPU EMAC accordingly.
164 * Requires active PHY maintenance mode.
166 static void emac_autoNegotiation(void)
171 // Wait for auto-negotation to complete
172 start = timer_clock();
174 reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMSR);
175 if (timer_clock() - start > 2000)
177 kprintf("eth error: auto-negotiation timeout\n");
181 while (!(reg & NIC_PHY_BMSR_ANCOMPL));
183 reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ANLPAR);
185 if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_TX_HDX))
187 LOG_INFO("eth: 100BASE-TX\n");
188 EMAC_NCFGR |= BV(EMAC_SPD);
192 LOG_INFO("eth: 10BASE-T\n");
193 EMAC_NCFGR &= ~BV(EMAC_SPD);
196 if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_10_FDX))
198 LOG_INFO("eth: full duplex\n");
199 EMAC_NCFGR |= BV(EMAC_FD);
203 LOG_INFO("eth: half duplex\n");
204 EMAC_NCFGR &= ~BV(EMAC_FD);
209 static int emac_reset(void)
213 PMC_PCER = BV(PIOA_ID);
214 PMC_PCER = BV(PIOB_ID);
215 PMC_PCER = BV(EMAC_ID);
217 // Disable TESTMODE and RMII
218 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
219 PIOB_PUDR = BV(PHY_COL_RMII_BIT);
221 // Disable PHY power down.
222 PIOB_PER = BV(PHY_PWRDN_BIT);
223 PIOB_OER = BV(PHY_PWRDN_BIT);
224 PIOB_CODR = BV(PHY_PWRDN_BIT);
226 pmc_periphEnable(PIOA_ID);
227 pmc_periphEnable(PIOB_ID);
228 pmc_periphEnable(PIOC_ID);
229 pmc_periphEnable(PIOD_ID);
230 pmc_periphEnable(EMAC_ID);
233 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
236 // Configure MII ports.
238 PIOB_ASR = PHY_MII_PINS;
240 PIOB_PDR = PHY_MII_PINS;
242 // Enable receive and transmit clocks.
243 EMAC_USRIO = BV(EMAC_CLKEN);
245 PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
246 PIOB_PDR = PHY_MII_PINS_PORTB;
248 // Enable receive, transmit clocks and RMII mode.
249 EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
252 // Enable management port.
253 EMAC_NCR |= BV(EMAC_MPE);
254 EMAC_NCFGR |= EMAC_CLK_HCLK_64;
256 // Set local MAC address.
257 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
258 (mac_addr[1] << 8) | mac_addr[0];
259 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
261 emac_autoNegotiation();
263 // Disable management port.
264 EMAC_NCR &= ~BV(EMAC_MPE);
270 static int emac_start(void)
275 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
277 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
278 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
280 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
282 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
284 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
285 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
286 tx_buf_tab[i].stat = TXS_USED;
288 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
290 /* Tell the EMAC where to find the descriptors. */
291 EMAC_RBQP = (uint32_t)rx_buf_tab;
292 EMAC_TBQP = (uint32_t)tx_buf_tab;
294 /* Clear receiver status. */
295 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
297 /* Copy all frames and discard FCS. */
298 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
300 /* Enable receiver, transmitter and statistics. */
301 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
306 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
312 ASSERT(len <= sizeof(tx_buf));
314 /* Check if the transmit buffer is available */
315 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
316 event_wait(&send_wait);
318 /* Copy the data into the buffer and prepare descriptor */
319 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
320 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
322 tx_buf_offset += wr_len;
327 void eth_sendFrame(void)
329 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
331 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
332 EMAC_NCR |= BV(EMAC_TSTART);
335 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
339 ssize_t eth_send(const uint8_t *buf, size_t len)
344 len = eth_putFrame(buf, len);
350 static void eth_buf_realign(int idx)
352 /* Empty buffer found. Realign. */
354 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
355 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
357 } while (idx != rx_buf_idx);
360 static size_t __eth_getFrameLen(void)
362 int idx, n = EMAC_RX_BUFFERS;
365 /* Skip empty buffers */
366 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
368 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
374 LOG_INFO("no frame found\n");
377 /* Search the start of frame and cleanup fragments */
378 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
379 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
381 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
382 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
388 LOG_INFO("no SOF found\n");
391 /* Search end of frame to evaluate the total frame size */
396 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
398 /* Empty buffer found. Realign. */
399 eth_buf_realign(idx);
402 if (rx_buf_tab[idx].stat & RXS_EOF)
403 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
404 if (UNLIKELY((idx != rx_buf_idx) &&
405 (rx_buf_tab[idx].stat & RXS_SOF)))
407 /* Another start of frame found. Realign. */
408 eth_buf_realign(idx);
411 if (++idx >= EMAC_RX_BUFFERS)
415 LOG_INFO("no EOF found\n");
419 size_t eth_getFrameLen(void)
423 /* Check if there is at least one available frame in the buffer */
426 len = __eth_getFrameLen();
429 /* Wait for RX interrupt */
430 event_wait(&recv_wait);
435 ssize_t eth_getFrame(uint8_t *buf, size_t len)
442 ASSERT(len <= sizeof(rx_buf));
444 /* Copy data from the RX buffer */
445 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
446 if (addr + len > &rx_buf[countof(rx_buf)])
448 size_t count = &rx_buf[countof(rx_buf)] - addr;
450 memcpy(buf, addr, count);
451 memcpy(buf + count, rx_buf, len - count);
455 memcpy(buf, addr, len);
457 /* Update descriptors */
460 if (len - rd_len >= EMAC_RX_BUFSIZ)
461 rd_len += EMAC_RX_BUFSIZ;
463 rd_len += len - rd_len;
464 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
466 LOG_INFO("bad frame found\n");
469 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
470 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
477 ssize_t eth_recv(uint8_t *buf, size_t len)
481 len = MIN(len, eth_getFrameLen());
482 return len ? eth_getFrame(buf, len) : 0;
492 event_initGeneric(&recv_wait);
493 event_initGeneric(&send_wait);
495 // Register interrupt vector
496 IRQ_SAVE_DISABLE(flags);
498 /* Disable all emac interrupts */
499 EMAC_IDR = 0xFFFFFFFF;
502 // TODO: define sysirq_set...
503 /* Set the vector. */
504 AIC_SVR(EMAC_ID) = emac_irqHandler;
505 /* Initialize to edge triggered with defined priority. */
506 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
507 /* Clear pending interrupt */
508 AIC_ICCR = BV(EMAC_ID);
509 /* Enable the system IRQ */
510 AIC_IECR = BV(EMAC_ID);
512 sysirq_setHandler(INT_EMAC, emac_irqHandler);
515 /* Enable interrupts */
516 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;