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29 * Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM family with Davicom 9161A phy.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
37 * \author Stefano Fedrigo <aleph@develer.com>
40 #include "cfg/cfg_eth.h"
42 #define LOG_LEVEL ETH_LOG_LEVEL
43 #define LOG_FORMAT ETH_LOG_FORMAT
47 #include <cfg/debug.h>
49 #include <cfg/macros.h>
50 #include <cfg/compiler.h>
52 // TODO: unify includes
53 //#include <io/at91sam7.h>
55 //#include <io/include.h>
57 #include <drv/irq_cm3.h>
59 #include <cpu/power.h>
60 #include <cpu/types.h>
63 #include <drv/timer.h>
66 #include <mware/event.h>
72 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
73 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
76 * MAC address configuration (please change this in your project!).
78 * TODO: make this paramater user-configurable from the Wizard.
80 const uint8_t mac_addr[] = { 0x00, 0x45, 0x56, 0x78, 0x9a, 0xbc };
82 /* Silent Doxygen bug... */
85 * NOTE: this buffer should be declared as 'volatile' because it is read by the
86 * hardware. However, this is accessed only via memcpy() that should guarantee
87 * coherency when copying from/to buffers.
89 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
90 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
93 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
94 * the hardware. However, this is accessed only via memcpy() that should
95 * guarantee coherency when copying from/to buffers.
97 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
98 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
101 static int tx_buf_idx;
102 static int tx_buf_offset;
103 static int rx_buf_idx;
105 static Event recv_wait, send_wait;
107 static DECLARE_ISR(emac_irqHandler)
109 /* Read interrupt status and disable interrupts. */
110 uint32_t isr = EMAC_ISR;
112 /* Receiver interrupt */
113 if ((isr & EMAC_RX_INTS))
115 if (isr & BV(EMAC_RCOMP))
116 event_do(&recv_wait);
117 EMAC_RSR = EMAC_RX_INTS;
119 /* Transmitter interrupt */
120 if (isr & EMAC_TX_INTS)
122 if (isr & BV(EMAC_TCOMP))
123 event_do(&send_wait);
124 EMAC_TSR = EMAC_TX_INTS;
130 * \brief Read contents of PHY register.
132 * \param reg PHY register number.
134 * \return Contents of the specified register.
136 static uint16_t phy_hw_read(uint8_t phy_addr, reg8_t reg)
139 EMAC_MAN = EMAC_SOF | EMAC_RW_READ
140 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
141 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
144 // Wait until PHY logic completed.
145 while (!(EMAC_NSR & BV(EMAC_IDLE)))
148 // Get data from PHY maintenance register.
149 return (uint16_t)(EMAC_MAN & EMAC_DATA);
154 * \brief Write value to PHY register.
156 * \param reg PHY register number.
157 * \param val Value to write.
159 static void phy_hw_write(uint8_t phy_addr, reg8_t reg, uint16_t val)
161 // PHY write command.
162 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE
163 | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
164 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
167 // Wait until PHY logic completed.
168 while (!(EMAC_NSR & BV(EMAC_IDLE)))
174 * Check link speed and duplex as negotiated by the PHY
175 * and configure CPU EMAC accordingly.
176 * Requires active PHY maintenance mode.
178 static void emac_autoNegotiation(void)
183 // Wait for auto-negotation to complete
184 start = timer_clock();
186 reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMSR);
187 if (timer_clock() - start > 2000)
189 kprintf("eth error: auto-negotiation timeout\n");
193 while (!(reg & NIC_PHY_BMSR_ANCOMPL));
195 reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ANLPAR);
197 if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_TX_HDX))
199 LOG_INFO("eth: 100BASE-TX\n");
200 EMAC_NCFGR |= BV(EMAC_SPD);
204 LOG_INFO("eth: 10BASE-T\n");
205 EMAC_NCFGR &= ~BV(EMAC_SPD);
208 if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_10_FDX))
210 LOG_INFO("eth: full duplex\n");
211 EMAC_NCFGR |= BV(EMAC_FD);
215 LOG_INFO("eth: half duplex\n");
216 EMAC_NCFGR &= ~BV(EMAC_FD);
221 static int emac_reset(void)
225 PMC_PCER = BV(PIOA_ID);
226 PMC_PCER = BV(PIOB_ID);
227 PMC_PCER = BV(EMAC_ID);
229 // Disable TESTMODE and RMII
230 PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
231 PIOB_PUDR = BV(PHY_COL_RMII_BIT);
233 // Disable PHY power down.
234 PIOB_PER = BV(PHY_PWRDN_BIT);
235 PIOB_OER = BV(PHY_PWRDN_BIT);
236 PIOB_CODR = BV(PHY_PWRDN_BIT);
238 pmc_periphEnable(PIOA_ID);
239 pmc_periphEnable(PIOB_ID);
240 pmc_periphEnable(PIOC_ID);
241 pmc_periphEnable(PIOD_ID);
242 pmc_periphEnable(EMAC_ID);
244 // Disable TESTMODE and RMII
245 PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
247 // Disable PHY power down.
248 PIOD_PER = BV(PHY_PWRDN_BIT);
249 PIOD_OER = BV(PHY_PWRDN_BIT);
250 PIOD_CODR = BV(PHY_PWRDN_BIT);
253 // Toggle external hardware reset pin.
254 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
255 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
257 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
260 // Configure MII ports.
262 PIOB_ASR = PHY_MII_PINS;
264 PIOB_PDR = PHY_MII_PINS;
266 // Enable receive and transmit clocks.
267 EMAC_USRIO = BV(EMAC_CLKEN);
269 PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
270 PIOB_PDR = PHY_MII_PINS_PORTB;
272 PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
273 PIOC_PDR = PHY_MII_PINS_PORTC;
275 // Enable receive, transmit clocks and RMII mode.
276 EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
279 // Enable management port.
280 EMAC_NCR |= BV(EMAC_MPE);
281 EMAC_NCFGR |= EMAC_CLK_HCLK_64;
283 // Set local MAC address.
284 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
285 (mac_addr[1] << 8) | mac_addr[0];
286 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
288 emac_autoNegotiation();
290 // Disable management port.
291 EMAC_NCR &= ~BV(EMAC_MPE);
297 static int emac_start(void)
302 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
304 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
305 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
307 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
309 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
311 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
312 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
313 tx_buf_tab[i].stat = TXS_USED;
315 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
317 /* Tell the EMAC where to find the descriptors. */
318 EMAC_RBQP = (uint32_t)rx_buf_tab;
319 EMAC_TBQP = (uint32_t)tx_buf_tab;
321 /* Clear receiver status. */
322 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
324 /* Copy all frames and discard FCS. */
325 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
327 /* Enable receiver, transmitter and statistics. */
328 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
333 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
339 ASSERT(len <= sizeof(tx_buf));
341 /* Check if the transmit buffer is available */
342 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
343 event_wait(&send_wait);
345 /* Copy the data into the buffer and prepare descriptor */
346 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
347 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
349 tx_buf_offset += wr_len;
354 void eth_sendFrame(void)
356 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
358 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
359 EMAC_NCR |= BV(EMAC_TSTART);
362 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
366 ssize_t eth_send(const uint8_t *buf, size_t len)
371 len = eth_putFrame(buf, len);
377 static void eth_buf_realign(int idx)
379 /* Empty buffer found. Realign. */
381 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
382 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
384 } while (idx != rx_buf_idx);
387 static size_t __eth_getFrameLen(void)
389 int idx, n = EMAC_RX_BUFFERS;
392 /* Skip empty buffers */
393 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
395 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
401 LOG_INFO("no frame found\n");
404 /* Search the start of frame and cleanup fragments */
405 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
406 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
408 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
409 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
415 LOG_INFO("no SOF found\n");
418 /* Search end of frame to evaluate the total frame size */
423 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
425 /* Empty buffer found. Realign. */
426 eth_buf_realign(idx);
429 if (rx_buf_tab[idx].stat & RXS_EOF)
430 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
431 if (UNLIKELY((idx != rx_buf_idx) &&
432 (rx_buf_tab[idx].stat & RXS_SOF)))
434 /* Another start of frame found. Realign. */
435 eth_buf_realign(idx);
438 if (++idx >= EMAC_RX_BUFFERS)
442 LOG_INFO("no EOF found\n");
446 size_t eth_getFrameLen(void)
450 /* Check if there is at least one available frame in the buffer */
453 len = __eth_getFrameLen();
456 /* Wait for RX interrupt */
457 event_wait(&recv_wait);
462 ssize_t eth_getFrame(uint8_t *buf, size_t len)
469 ASSERT(len <= sizeof(rx_buf));
471 /* Copy data from the RX buffer */
472 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
473 if (addr + len > &rx_buf[countof(rx_buf)])
475 size_t count = &rx_buf[countof(rx_buf)] - addr;
477 memcpy(buf, addr, count);
478 memcpy(buf + count, rx_buf, len - count);
482 memcpy(buf, addr, len);
484 /* Update descriptors */
487 if (len - rd_len >= EMAC_RX_BUFSIZ)
488 rd_len += EMAC_RX_BUFSIZ;
490 rd_len += len - rd_len;
491 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
493 LOG_INFO("bad frame found\n");
496 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
497 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
504 ssize_t eth_recv(uint8_t *buf, size_t len)
508 len = MIN(len, eth_getFrameLen());
509 return len ? eth_getFrame(buf, len) : 0;
519 event_initGeneric(&recv_wait);
520 event_initGeneric(&send_wait);
522 // Register interrupt vector
523 IRQ_SAVE_DISABLE(flags);
525 /* Disable all emac interrupts */
526 EMAC_IDR = 0xFFFFFFFF;
529 // TODO: define sysirq_set...
530 /* Set the vector. */
531 AIC_SVR(EMAC_ID) = emac_irqHandler;
532 /* Initialize to edge triggered with defined priority. */
533 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
534 /* Clear pending interrupt */
535 AIC_ICCR = BV(EMAC_ID);
536 /* Enable the system IRQ */
537 AIC_IECR = BV(EMAC_ID);
539 sysirq_setHandler(INT_EMAC, emac_irqHandler);
542 /* Enable interrupts */
543 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;