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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief HSMCI driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "hsmci_sam3.h"
40 #include <drv/timer.h>
42 #include <drv/irq_cm3.h>
48 #define HSMCI_INIT_SPEED 400000
49 #define HSMCI_CLK_DIV ((CPU_FREQ / (HSMCI_INIT_SPEED << 1)) - 1)
51 #define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \
52 BV(HSMCI_SR_RDIRE) | \
53 BV(HSMCI_SR_RCRCE) | \
54 BV(HSMCI_SR_RENDE) | \
56 BV(HSMCI_SR_DCRCE) | \
58 BV(HSMCI_SR_CSTOE) | \
59 BV(HSMCI_SR_BLKOVRE) | \
63 #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
64 | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
66 #define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
70 } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
73 #define HSMCI_WAIT_DATA_RDY()\
76 } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
78 #define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK)
80 #define HSMCI_HW_INIT() \
82 PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \
83 PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \
87 #define STROBE_ON() PIOB_SODR = BV(13)
88 #define STROBE_OFF() PIOB_CODR = BV(13)
89 #define STROBE_INIT() \
95 static DECLARE_ISR(hsmci_irq)
97 if (HSMCI_SR & BV(HSMCI_IER_RTOE))
100 HSMCI_CMDR = 0 | HSMCI_CMDR_RSPTYP_NORESP | BV(HSMCI_CMDR_OPDCMD);
104 void hsmci_readResp(void *resp, size_t len)
107 uint32_t *r = (uint32_t *)resp;
109 for (size_t i = 0; i < len ; i++)
113 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
118 HSMCI_ARGR = argument;
119 HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT) | BV(HSMCI_CMDR_OPDCMD);
121 uint32_t status = HSMCI_SR;
122 while (!(status & BV(HSMCI_SR_CMDRDY)))
124 if (status & HSMCI_RESP_ERROR_MASK)
136 void hsmci_setBlkSize(size_t blk_size)
138 HSMCI_DMA = BV(HSMCI_DMA_DMAEN);
139 HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT);
142 bool hsmci_read(uint32_t *buf, size_t word_num)
145 ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
147 kprintf("DMAC status %08lx channel st %08lx\n", DMAC_EBCISR, DMAC_CHSR);
149 DMAC_SADDR0 = 0x40000200U;
150 DMAC_DADDR0 = (uint32_t)buf;
153 DMAC_CTRLA0 = word_num | DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
154 DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
155 DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
157 ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
158 DMAC_CHER = BV(DMAC_CHER_ENA0);
160 while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
163 DMAC_CHDR = BV(DMAC_CHDR_DIS0);
167 void hsmci_init(Hsmci *hsmci)
174 pmc_periphEnable(HSMCI_ID);
175 HSMCI_CR = BV(HSMCI_CR_SWRST);
176 HSMCI_CR = BV(HSMCI_CR_PWSDIS) | BV(HSMCI_CR_MCIDIS);
177 HSMCI_IDR = 0xFFFFFFFF;
179 HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
180 HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
181 HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
183 HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
185 sysirq_setHandler(INT_HSMCI, hsmci_irq);
186 HSMCI_CR = BV(HSMCI_CR_MCIEN);
187 HSMCI_DMA &= ~BV(HSMCI_DMA_DMAEN);
190 DMAC_EBCIDR = 0x3FFFFF;
191 DMAC_CHDR = BV(DMAC_CHDR_DIS0);
194 DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | BV(DMAC_CFG_SOD);
196 pmc_periphEnable(DMAC_ID);
197 DMAC_EN = BV(DMAC_EN_ENABLE);
199 //HSMCI_IER = BV(HSMCI_IER_RTOE);