4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief HSMCI driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "hsmci_sam3.h"
40 #include <drv/timer.h>
42 #include <drv/irq_cm3.h>
48 #define HSMCI_INIT_SPEED 400000
49 #define HSMCI_CLK_DIV ((CPU_FREQ / (HSMCI_INIT_SPEED << 1)) - 1)
51 #define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \
52 BV(HSMCI_SR_RDIRE) | \
53 BV(HSMCI_SR_RCRCE) | \
54 BV(HSMCI_SR_RENDE) | \
56 BV(HSMCI_SR_DCRCE) | \
58 BV(HSMCI_SR_CSTOE) | \
59 BV(HSMCI_SR_BLKOVRE) | \
63 #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
64 | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
66 #define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
70 } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
72 #define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK)
74 #define HSMCI_HW_INIT() \
76 PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \
77 PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \
81 #define STROBE_ON() PIOB_SODR = BV(13)
82 #define STROBE_OFF() PIOB_CODR = BV(13)
83 #define STROBE_INIT() \
89 static DECLARE_ISR(hsmci_irq)
91 if (HSMCI_SR & BV(HSMCI_IER_RTOE))
94 HSMCI_CMDR = 0 | HSMCI_CMDR_RSPTYP_NORESP | BV(HSMCI_CMDR_OPDCMD);
98 void hsmci_readResp(void *resp, size_t len)
101 uint32_t *r = (uint32_t *)resp;
103 for (size_t i = 0; i < len ; i++)
107 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
112 HSMCI_ARGR = argument;
113 HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT) | BV(HSMCI_CMDR_OPDCMD);
115 uint32_t status = HSMCI_SR;
116 while (!(status & BV(HSMCI_SR_CMDRDY)))
118 if (status & HSMCI_RESP_ERROR_MASK)
130 void hsmci_init(Hsmci *hsmci)
137 pmc_periphEnable(HSMCI_ID);
138 HSMCI_CR = BV(HSMCI_CR_SWRST);
139 HSMCI_CR = BV(HSMCI_CR_PWSDIS) | BV(HSMCI_CR_MCIDIS);
140 HSMCI_IDR = 0xFFFFFFFF;
142 HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
143 HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
144 HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
146 HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
148 sysirq_setHandler(INT_HSMCI, hsmci_irq);
149 HSMCI_CR = BV(HSMCI_CR_MCIEN);
150 //HSMCI_IER = BV(HSMCI_IER_RTOE);