4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the LM3S I2C (implementation)
37 #include "cfg/cfg_i2c.h"
39 #define LOG_LEVEL I2C_LOG_LEVEL
40 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <cpu/detect.h>
50 #include <cpu/types.h>
54 #include <drv/timer.h>
56 #include <drv/gpio_lm3s.h>
57 #include <drv/clock_lm3s.h>
70 static void i2c_lm3s_start(struct I2c *i2c, uint16_t slave_addr)
72 i2c->hw->first_send = true;
74 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
75 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr & ~BV(0);
76 else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
77 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr | BV(0);
80 INLINE bool wait_addrAck(I2c *i2c, uint32_t mode_mask)
82 ticks_t start = timer_clock();
85 uint32_t status = HWREG(i2c->hw->base + I2C_O_MCS);
87 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
90 if (status & I2C_MCS_ADRACK)
92 HWREG(i2c->hw->base + I2C_O_MCS) = mode_mask;
93 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
102 static void i2c_lm3s_put(I2c *i2c, const uint8_t data)
104 if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
106 HWREG(i2c->hw->base + I2C_O_MDR) = data;
107 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
108 while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
110 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
112 LOG_ERR("Start timeout\n");
113 i2c->errors |= I2C_START_TIMEOUT;
114 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
115 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
119 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
121 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
122 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
125 i2c->hw->first_send = false;
130 HWREG(i2c->hw->base + I2C_O_MDR) = data;
131 if (i2c->hw->first_send)
133 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
134 while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
136 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
138 LOG_ERR("Start timeout\n");
139 i2c->errors |= I2C_START_TIMEOUT;
140 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
141 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
145 i2c->hw->first_send = false;
150 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
151 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
153 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
155 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
156 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
162 static uint8_t i2c_lm3s_get(I2c *i2c)
164 if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
166 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
167 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
170 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
172 LOG_ERR("Start timeout\n");
173 i2c->errors |= I2C_START_TIMEOUT;
174 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
178 uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
180 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
182 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
183 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
186 i2c->hw->first_send = false;
191 if (i2c->hw->first_send)
193 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START;
194 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
196 if (!wait_addrAck(i2c, I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START))
198 LOG_ERR("Start timeout\n");
199 i2c->errors |= I2C_START_TIMEOUT;
200 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
204 i2c->hw->first_send = false;
205 return HWREG(i2c->hw->base + I2C_O_MDR);
209 if (i2c->xfer_size > 1)
210 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN;
212 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
214 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
215 uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
217 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
219 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
220 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
231 static const I2cVT i2c_lm3s_vt =
233 .start = i2c_lm3s_start,
240 struct I2cHardware i2c_lm3s_hw[] =
243 .base = I2C0_MASTER_BASE,
244 .sys_cntl = SYSCTL_RCGC1_I2C0,
245 .sys_gpio = SYSCTL_RCGC2_GPIOB,
246 .pin_mask = (GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN),
247 .gpio_base = GPIO_PORTB_BASE,
250 .base = I2C1_MASTER_BASE,
251 .sys_cntl = SYSCTL_RCGC1_I2C1,
252 .sys_gpio = SYSCTL_RCGC2_GPIOA,
253 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
254 .gpio_base = GPIO_PORTA_BASE,
259 * Initialize I2C module.
261 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
263 i2c->hw = &i2c_lm3s_hw[dev];
264 i2c->vt = &i2c_lm3s_vt;
266 /* Enable the peripheral clock */
267 SYSCTL_RCGC1_R |= i2c->hw->sys_cntl;
268 SYSCTL_RCGC2_R |= i2c->hw->sys_gpio;
270 /* Configure GPIO pins to work as I2C pins */
271 lm3s_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask,
272 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
274 * Note: to set correctly the i2c speed we shold before enable the i2c
275 * device and then set in master time period the correct value
278 /* Enable i2c device */
279 HWREG(i2c->hw->base + I2C_O_MCR) |= I2C_MCR_MFE;
282 * Compute the clock divider that achieves the fastest speed less than or
283 * equal to the desired speed. The numerator is biased to favor a larger
284 * clock divider so that the resulting clock is always less than or equal
285 * to the desired clock, never greater.
287 HWREG(i2c->hw->base + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * clock) - 1) / (2 * 10 * clock)) - 1;