c74a667ed4c320046cbbbd2e00b9a0e155315662
[bertos.git] / bertos / cpu / cortex-m3 / drv / i2c_lm3s.c
1 /**
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9  * (at your option) any later version.
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25  * the GNU General Public License.  This exception does not however
26  * invalidate any other reasons why the executable file might be covered by
27  * the GNU General Public License.
28  *
29  * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30  *
31  * -->
32  *
33  * \brief Driver for the LM3S I2C (implementation)
34  *
35  */
36
37 #include "cfg/cfg_i2c.h"
38
39 #define LOG_LEVEL  I2C_LOG_LEVEL
40 #define LOG_FORMAT I2C_LOG_FORMAT
41
42 #include <cfg/log.h>
43
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
47
48 #include <cpu/detect.h>
49 #include <cpu/irq.h>
50 #include <cpu/types.h>
51
52 #include <io/lm3s.h>
53
54 #include <drv/timer.h>
55 #include <drv/i2c.h>
56 #include <drv/gpio_lm3s.h>
57 #include <drv/clock_lm3s.h>
58
59
60 struct I2cHardware
61 {
62         uint32_t base;
63         uint32_t sys_cntl;
64         uint32_t sys_gpio;
65         uint32_t pin_mask;
66         uint32_t gpio_base;
67         bool first_send;
68 };
69
70 static void i2c_lm3s_start(struct I2c *i2c, uint16_t slave_addr)
71 {
72         i2c->hw->first_send = true;
73
74         if (I2C_TEST_START(i2c->flags) == I2C_START_W)
75                 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr & ~BV(0);
76         else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
77                 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr | BV(0);
78 }
79
80 INLINE bool wait_addrAck(I2c *i2c, uint32_t mode_mask)
81 {
82         ticks_t start = timer_clock();
83         while (1)
84         {
85                 uint32_t status = HWREG(i2c->hw->base + I2C_O_MCS);
86
87                 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
88                         return false;
89
90                 if (status & I2C_MCS_ADRACK)
91                 {
92                         HWREG(i2c->hw->base + I2C_O_MCS) = mode_mask;
93                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
94                         continue;
95                 }
96                 else
97                         break;
98         }
99         return true;
100 }
101
102 static void i2c_lm3s_put(I2c *i2c, const uint8_t data)
103 {
104         if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
105         {
106                 HWREG(i2c->hw->base + I2C_O_MDR) = data;
107                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
108                 while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
109
110                 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
111                 {
112                         LOG_ERR("Start timeout\n");
113                         i2c->errors |= I2C_START_TIMEOUT;
114                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
115                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
116                         return;
117                 }
118
119                 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
120                 {
121                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
122                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
123                 }
124
125                 i2c->hw->first_send = false;
126                 return;
127         }
128         else
129         {
130                 HWREG(i2c->hw->base + I2C_O_MDR) = data;
131                 if (i2c->hw->first_send)
132                 {
133                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
134                         while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
135
136                         if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
137                         {
138                                 LOG_ERR("Start timeout\n");
139                                 i2c->errors |= I2C_START_TIMEOUT;
140                                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
141                                 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
142                                 return;
143                         }
144
145                         i2c->hw->first_send = false;
146                         return;
147                 }
148                 else
149                 {
150                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
151                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
152
153                         if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
154                         {
155                                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
156                                 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
157                         }
158                 }
159         }
160 }
161
162 static uint8_t i2c_lm3s_get(I2c *i2c)
163 {
164         if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
165         {
166                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
167                 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
168
169
170                 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
171                 {
172                         LOG_ERR("Start timeout\n");
173                         i2c->errors |= I2C_START_TIMEOUT;
174                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
175                         return 0xFF;
176                 }
177
178                 uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
179
180                 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
181                 {
182                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
183                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
184                 }
185
186                 i2c->hw->first_send = false;
187                 return data;
188         }
189         else
190         {
191                 if (i2c->hw->first_send)
192                 {
193                         HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START;
194                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
195
196                         if (!wait_addrAck(i2c, I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START))
197                         {
198                                 LOG_ERR("Start timeout\n");
199                                 i2c->errors |= I2C_START_TIMEOUT;
200                                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
201                                 return 0xFF;
202                         }
203
204                         i2c->hw->first_send = false;
205                         return HWREG(i2c->hw->base + I2C_O_MDR);
206                 }
207                 else
208                 {
209                         if (i2c->xfer_size > 1)
210                                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN;
211                         else
212                                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
213
214                         while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
215                         uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
216
217                         if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
218                         {
219                                 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
220                                 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
221                         }
222
223                         return data;
224                 }
225         }
226         return 0xFF;
227 }
228
229 MOD_DEFINE(i2c);
230
231 static const I2cVT i2c_lm3s_vt =
232 {
233         .start = i2c_lm3s_start,
234         .get = i2c_lm3s_get,
235         .put = i2c_lm3s_put,
236         .send = i2c_swSend,
237         .recv = i2c_swRecv,
238 };
239
240 struct I2cHardware i2c_lm3s_hw[] =
241 {
242         { /* I2C0 */
243                 .base = I2C0_MASTER_BASE,
244                 .sys_cntl = SYSCTL_RCGC1_I2C0,
245                 .sys_gpio = SYSCTL_RCGC2_GPIOB,
246                 .pin_mask = (GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN),
247                 .gpio_base = GPIO_PORTB_BASE,
248         },
249         { /* I2C1 */
250                 .base = I2C1_MASTER_BASE,
251                 .sys_cntl = SYSCTL_RCGC1_I2C1,
252                 .sys_gpio = SYSCTL_RCGC2_GPIOA,
253                 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
254                 .gpio_base = GPIO_PORTA_BASE,
255         },
256 };
257
258 /**
259  * Initialize I2C module.
260  */
261 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
262 {
263         i2c->hw = &i2c_lm3s_hw[dev];
264         i2c->vt = &i2c_lm3s_vt;
265
266         /* Enable the peripheral clock */
267         SYSCTL_RCGC1_R |= i2c->hw->sys_cntl;
268         SYSCTL_RCGC2_R |= i2c->hw->sys_gpio;
269
270         /* Configure GPIO pins to work as I2C pins */
271         lm3s_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask,
272                 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
273         /*
274          * Note: to set correctly the i2c speed we shold before enable the i2c
275          * device and then set in master time period the correct value
276          */
277
278         /* Enable i2c device */
279         HWREG(i2c->hw->base + I2C_O_MCR) |= I2C_MCR_MFE;
280
281     /*
282          * Compute the clock divider that achieves the fastest speed less than or
283      * equal to the desired speed.  The numerator is biased to favor a larger
284      * clock divider so that the resulting clock is always less than or equal
285      * to the desired clock, never greater.
286          */
287     HWREG(i2c->hw->base + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * clock) - 1) / (2 * 10 * clock)) - 1;
288
289         MOD_INIT(i2c);
290 }