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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the LM3S I2C (implementation)
37 #include "cfg/cfg_i2c.h"
39 #define LOG_LEVEL I2C_LOG_LEVEL
40 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <cpu/detect.h>
51 #include <io/cm3_types.h>
54 #include <drv/timer.h>
56 #include <drv/gpio_lm3s.h>
57 #include <drv/clock_lm3s.h>
60 #define I2C I2C0_MASTER_BASE
63 * Send START condition on the bus.
65 * \return true on success, false otherwise.
67 static bool i2c_builtin_start(void)
74 * Send START condition and select slave for write.
75 * \c id is the device id comprehensive of address left shifted by 1.
76 * The LSB of \c id is ignored and reset to 0 for write operation.
78 * \return true on success, false otherwise.
80 bool i2c_builtin_start_w(uint8_t id)
83 HWREG(I2C + I2C_O_MSA) = (id << 1) | BV(I2C_MSA_ADDS);
90 * Send START condition and select slave for read.
91 * \c id is the device id comprehensive of address left shifted by 1.
92 * The LSB of \c id is ignored and set to 1 for read operation.
94 * \return true on success, false otherwise.
96 bool i2c_builtin_start_r(uint8_t id)
98 HWREG(I2C + I2C_O_MSA) = (id << 1) | BV(I2C_MSA_ADDR);
105 * Send STOP condition.
107 void i2c_builtin_stop(void)
114 * Put a single byte in master transmitter mode
115 * to the selected slave device through the TWI bus.
117 * \return true on success, false on error.
119 bool i2c_builtin_put(const uint8_t data)
125 * Get 1 byte from slave in master transmitter mode
126 * to the selected slave device through the I2C bus.
127 * If \a ack is true issue a ACK after getting the byte,
128 * otherwise a NACK is issued.
130 * \return the byte read if ok, EOF on errors.
132 int i2c_builtin_get(bool ack)
144 /* avoid sign extension */
149 INLINE bool check_i2cStatus(uint32_t base)
151 ticks_t start = timer_clock();
157 uint32_t status = HWREG(base + I2C_O_MCS);
159 if (status & I2C_MCS_ADRACK)
160 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
162 LOG_ERR("Timeout on I2C_START\n");
166 if (status & I2C_MCS_BUSY)
176 bool i2c_send(const void *_buf, size_t count)
178 const uint8_t *buf = (const uint8_t *)_buf;
182 HWREG(I2C + I2C_O_MDR) = *buf++;
184 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_SINGLE_SEND;
186 if ( !check_i2cStatus(I2C) )
194 HWREG(I2C + I2C_O_MDR) = *buf++;
197 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_START;
199 if ( !check_i2cStatus(I2C) )
204 HWREG(I2C + I2C_O_MDR) = *buf++;
205 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_CONT;
207 if ( !check_i2cStatus(I2C) )
213 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_SEND_FINISH;
215 if ( !check_i2cStatus(I2C) )
224 * In order to read bytes from the i2c we should make some tricks.
225 * This because the silicon manage automatically the NACK on last byte, so to read
226 * one, two or three byte we should manage separately these cases.
228 bool i2c_recv(void *_buf, size_t count)
230 uint8_t *buf = (const uint8_t *)_buf;
234 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_SINGLE_RECEIVE;
236 if ( !check_i2cStatus(I2C) )
239 *buf++ = HWREGB(I2C + I2C_O_MDR);
245 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_START;
247 if ( !check_i2cStatus(I2C) )
252 *buf++ = HWREGB(I2C + I2C_O_MDR);
254 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_CONT;
256 if ( !check_i2cStatus(I2C) )
262 HWREG(I2C + I2C_O_MCS) = I2C_MASTER_CMD_BURST_RECEIVE_FINISH;
264 if ( !check_i2cStatus(I2C) )
267 *buf++ = HWREGB(I2C + I2C_O_MDR);
276 * Initialize I2C module.
278 void i2c_builtin_init(void)
281 /* Enable the peripheral clock */
282 SYSCTL_RCGC1_R |= SYSCTL_RCGC1_I2C0;
283 SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOB;
286 /* Configure GPIO pins to work as I2C pins */
287 lm3s_gpioPinConfig(GPIO_PORTB_BASE, GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN,
288 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
290 //Enable I2C in master mode
291 HWREG(I2C + I2C_O_MCR) |= I2C_MCR_MFE;
294 * Compute the clock divider that achieves the fastest speed less than or
295 * equal to the desired speed. The numerator is biased to favor a larger
296 * clock divider so that the resulting clock is always less than or equal
297 * to the desired clock, never greater.
299 HWREG(I2C + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * CONFIG_I2C_FREQ) - 1) / (2 * 10 * CONFIG_I2C_FREQ)) - 1;