4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the LM3S I2C (implementation)
37 #include "cfg/cfg_i2c.h"
39 #define LOG_LEVEL I2C_LOG_LEVEL
40 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <cpu/detect.h>
50 #include <cpu/types.h>
54 #include <drv/timer.h>
56 #include <drv/gpio_lm3s.h>
57 #include <drv/clock_lm3s.h>
70 static void i2c_lm3s_start(struct I2c *i2c, uint16_t slave_addr)
72 i2c->hw->first_send = true;
74 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
75 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr & ~BV(0);
76 else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
77 HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr | BV(0);
80 INLINE bool wait_addrAck(I2c *i2c, uint32_t mode_mask)
82 ticks_t start = timer_clock();
85 uint32_t status = HWREG(i2c->hw->base + I2C_O_MCS);
87 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
90 if (status & I2C_MCS_ADRACK)
92 HWREG(i2c->hw->base + I2C_O_MCS) = mode_mask;
93 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
102 static void i2c_lm3s_put(I2c *i2c, const uint8_t data)
104 HWREG(i2c->hw->base + I2C_O_MDR) = data;
106 if (i2c->hw->first_send)
108 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
109 while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
111 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
113 LOG_ERR("Start timeout\n");
114 i2c->errors |= I2C_START_TIMEOUT;
115 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
116 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
120 i2c->hw->first_send = false;
124 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
125 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
128 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
130 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
131 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
135 static uint8_t i2c_lm3s_get(I2c *i2c)
137 if ((i2c->xfer_size == 1) && (i2c->hw->first_send))
139 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START;
140 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
143 if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START))
145 LOG_ERR("Start timeout\n");
146 i2c->errors |= I2C_START_TIMEOUT;
147 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
151 uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
153 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
155 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
156 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
159 i2c->hw->first_send = false;
164 if (i2c->hw->first_send)
166 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START;
167 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY);
169 if (!wait_addrAck(i2c, I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START))
171 LOG_ERR("Start timeout\n");
172 i2c->errors |= I2C_START_TIMEOUT;
173 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
177 i2c->hw->first_send = false;
178 return HWREG(i2c->hw->base + I2C_O_MDR);
182 if (i2c->xfer_size > 1)
183 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN;
185 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN;
187 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
188 uint8_t data = HWREG(i2c->hw->base + I2C_O_MDR);
190 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
192 HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP;
193 while (HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY );
204 static const I2cVT i2c_lm3s_vt =
206 .start = i2c_lm3s_start,
213 struct I2cHardware i2c_lm3s_hw[] =
216 .base = I2C0_MASTER_BASE,
217 .sys_cntl = SYSCTL_RCGC1_I2C0,
218 .sys_gpio = SYSCTL_RCGC2_GPIOB,
219 .pin_mask = (GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN),
220 .gpio_base = GPIO_PORTB_BASE,
223 .base = I2C1_MASTER_BASE,
224 .sys_cntl = SYSCTL_RCGC1_I2C1,
225 .sys_gpio = SYSCTL_RCGC2_GPIOA,
226 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
227 .gpio_base = GPIO_PORTA_BASE,
232 * Initialize I2C module.
234 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
236 i2c->hw = &i2c_lm3s_hw[dev];
237 i2c->vt = &i2c_lm3s_vt;
239 /* Enable the peripheral clock */
240 SYSCTL_RCGC1_R |= i2c->hw->sys_cntl;
241 SYSCTL_RCGC2_R |= i2c->hw->sys_gpio;
243 /* Configure GPIO pins to work as I2C pins */
244 lm3s_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask,
245 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
247 * Note: to set correctly the i2c speed we shold before enable the i2c
248 * device and then set in master time period the correct value
251 /* Enable i2c device */
252 HWREG(i2c->hw->base + I2C_O_MCR) |= I2C_MCR_MFE;
255 * Compute the clock divider that achieves the fastest speed less than or
256 * equal to the desired speed. The numerator is biased to favor a larger
257 * clock divider so that the resulting clock is always less than or equal
258 * to the desired clock, never greater.
260 HWREG(i2c->hw->base + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * clock) - 1) / (2 * 10 * clock)) - 1;