4 * This file is part of BeRTOS.
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief TWI driver for SAM3 (implementation)
35 * Only master mode is supported.
37 * \author Stefano Fedrigo <aleph@develer.com>
41 #include "cfg/cfg_i2c.h"
43 #define LOG_LEVEL I2C_LOG_LEVEL
44 #define LOG_FORMAT I2C_LOG_FORMAT
48 #include <hw/hw_cpufreq.h> // CPU_FREQ
49 #include <cfg/debug.h>
50 #include <cfg/macros.h> // BV()
51 #include <cfg/module.h>
52 #include <cpu/detect.h>
54 #include <cpu/power.h>
55 #include <drv/timer.h>
67 INLINE bool waitTxRdy(I2c *i2c, time_t ms_timeout)
69 ticks_t start = timer_clock();
71 while (!(HWREG(i2c->hw->base + TWI_SR_OFF) & TWI_SR_TXRDY))
73 if (timer_clock() - start > ms_to_ticks(ms_timeout))
81 INLINE bool waitRxRdy(I2c *i2c, time_t ms_timeout)
83 ticks_t start = timer_clock();
85 while (!(HWREG(i2c->hw->base + TWI_SR_OFF) & TWI_SR_RXRDY))
87 if (timer_clock() - start > ms_to_ticks(ms_timeout))
95 INLINE void waitXferComplete(I2c *i2c)
97 while (!(HWREG(i2c->hw->base + TWI_SR_OFF) & TWI_SR_TXCOMP))
102 * Set STOP condition bit, to send stop after next sent byte.
104 INLINE void setStop(I2c *i2c)
106 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_STOP;
110 * The start is not performed when we call the start function
111 * because the hardware should know the first data byte to send.
112 * Generally to perform a byte send we should write the slave address
113 * in slave address register and the first byte to send in data registry.
114 * After then we can perform the start write procedure, and send really
115 * the our data. To use common bertos i2c api the really start will be
116 * performed when the user "put" or "send" its data. These tricks are hide
117 * from the driver implementation.
119 static void i2c_sam3_start(struct I2c *i2c, uint16_t slave_addr)
121 i2c->hw->first_xtranf = true;
123 if (I2C_TEST_START(i2c->flags) == I2C_START_R)
124 HWREG(i2c->hw->base + TWI_MMR_OFF) = TWI_MMR_DADR(slave_addr >> 1) | TWI_MMR_MREAD;
126 HWREG(i2c->hw->base + TWI_MMR_OFF) = TWI_MMR_DADR(slave_addr >> 1);
129 static void i2c_sam3_putc(I2c *i2c, const uint8_t data)
131 if (!waitTxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
133 LOG_ERR("i2c: txready timeout\n");
134 i2c->errors |= I2C_START_TIMEOUT;
138 HWREG(i2c->hw->base + TWI_THR_OFF) = data;
140 // On first byte sent wait for start timeout
141 if (i2c->hw->first_xtranf && !waitTxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
143 LOG_ERR("i2c: write start timeout\n");
144 i2c->errors |= I2C_START_TIMEOUT;
146 waitXferComplete(i2c);
149 i2c->hw->first_xtranf = false;
151 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
154 waitXferComplete(i2c);
158 static uint8_t i2c_sam3_getc(I2c *i2c)
162 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
165 if (i2c->hw->first_xtranf)
167 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_START;
168 i2c->hw->first_xtranf = false;
171 if (!waitRxRdy(i2c, CONFIG_I2C_START_TIMEOUT))
173 LOG_ERR("i2c: read start timeout\n");
174 i2c->errors |= I2C_START_TIMEOUT;
178 data = HWREG(i2c->hw->base + TWI_RHR_OFF);
180 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
181 waitXferComplete(i2c);
186 static void i2c_setClock(I2c *i2c, int clock)
193 cl_div = ((CPU_FREQ / (2 * clock)) - 4) / (1 << ck_div);
202 LOG_INFO("i2c: using CKDIV = %lu and CLDIV/CHDIV = %lu\n\n", ck_div, cl_div);
204 HWREG(i2c->hw->base + TWI_CWGR_OFF) = 0;
205 HWREG(i2c->hw->base + TWI_CWGR_OFF) = (ck_div << 16) | (cl_div << 8) | cl_div;
209 static const I2cVT i2c_sam3_vt =
211 .start = i2c_sam3_start,
212 .getc = i2c_sam3_getc,
213 .putc = i2c_sam3_putc,
214 .write = i2c_genericWrite,
215 .read = i2c_genericRead,
218 struct I2cHardware i2c_sam3_hw[I2C_CNT];
222 * Initialize I2C module.
224 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
228 ASSERT(dev < I2C_CNT);
230 i2c->hw = &i2c_sam3_hw[dev];
231 i2c->vt = &i2c_sam3_vt;
233 // Configure I/O pins
234 pmc_periphEnable(PIOA_ID);
239 i2c->hw->base = TWI0_BASE;
240 PIO_PERIPH_SEL(TWI0_PORT, BV(TWI0_TWD) | BV(TWI0_TWCK), TWI0_PERIPH);
241 HWREG(TWI0_PORT + PIO_PDR_OFF) = BV(TWI0_TWD) | BV(TWI0_TWCK);
242 pmc_periphEnable(TWI0_ID);
245 i2c->hw->base = TWI1_BASE;
246 PIO_PERIPH_SEL(TWI1_PORT, BV(TWI1_TWD) | BV(TWI1_TWCK), TWI1_PERIPH);
247 HWREG(TWI1_PORT + PIO_PDR_OFF) = BV(TWI1_TWD) | BV(TWI1_TWCK);
248 pmc_periphEnable(TWI1_ID);
251 ASSERT(!"i2c: invalid dev number");
256 * Reset sequence: enable slave mode, reset, read RHR,
257 * disable slave and master modes.
259 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SVEN;
260 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SWRST;
261 dummy = HWREG(i2c->hw->base + TWI_RHR_OFF);
262 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_SVDIS;
263 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSDIS;
266 HWREG(i2c->hw->base + TWI_CR_OFF) = TWI_CR_MSEN;
268 i2c_setClock(i2c, clock);