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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32F103xx I2C driver.
35 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2c.h"
40 #define LOG_LEVEL I2C_LOG_LEVEL
41 #define LOG_FORMAT I2C_LOG_FORMAT
44 #include <cfg/debug.h>
45 #include <cfg/macros.h> // BV()
46 #include <cfg/module.h>
48 #include <drv/gpio_stm32.h>
49 #include <drv/irq_cm3.h>
50 #include <drv/clock_stm32.h>
52 #include <drv/timer.h>
56 struct stm32_i2c *i2c = (struct stm32_i2c *)I2C1_BASE;
59 #define WAIT_BTF(base) while( !(base->SR1 & BV(SR1_BTF)) )
60 #define WAIT_RXE(base) while( !(base->SR1 & BV(SR1_RXE)) )
62 INLINE uint32_t get_status(struct stm32_i2c *base)
64 return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
68 INLINE bool check_i2cStatus(uint32_t event)
72 uint32_t stat = get_status(i2c);
77 if (stat & SR1_ERR_MASK)
79 LOG_ERR("[%08lx]\n", stat & SR1_ERR_MASK);
80 i2c->SR1 &= ~SR1_ERR_MASK;
82 i2c->CR1 |= CR1_START_SET;
92 * Send START condition on the bus.
94 * \return true on success, false otherwise.
96 static bool i2c_builtin_start(void)
99 i2c->CR1 |= CR1_ACK_SET | CR1_PE_SET | CR1_START_SET;
101 if(check_i2cStatus(I2C_EVENT_MASTER_MODE_SELECT))
109 * Send START condition and select slave for write.
110 * \c id is the device id comprehensive of address left shifted by 1.
111 * The LSB of \c id is ignored and reset to 0 for write operation.
113 * \return true on success, false otherwise.
115 bool i2c_builtin_start_w(uint8_t id)
119 * Loop on the select write sequence: when the eeprom is busy
120 * writing previously sent data it will reply to the SLA_W
121 * control byte with a NACK. In this case, we must
122 * keep trying until the eeprom responds with an ACK.
124 ticks_t start = timer_clock();
125 while (i2c_builtin_start())
127 i2c->DR = id & OAR1_ADD0_RESET;
129 if(check_i2cStatus(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
132 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
134 LOG_ERR("Timeout on I2C_START\n");
144 * Send START condition and select slave for read.
145 * \c id is the device id comprehensive of address left shifted by 1.
146 * The LSB of \c id is ignored and set to 1 for read operation.
148 * \return true on success, false otherwise.
150 bool i2c_builtin_start_r(uint8_t id)
154 i2c->DR = (id | OAR1_ADD0_SET);
156 if(check_i2cStatus(I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
164 * Send STOP condition.
166 void i2c_builtin_stop(void)
168 i2c->CR1 |= CR1_STOP_SET;
169 i2c->CR1 &= CR1_PE_RESET;
174 bool i2c_builtin_put(const uint8_t data)
180 if(check_i2cStatus(I2C_EVENT_MASTER_BYTE_TRANSMITTED))
186 int i2c_builtin_get(bool ack)
193 * In order to read bytes from the i2c we should make some tricks.
194 * This because the silicon manage automatically the NACK on last byte, so to read
195 * one, two or three byte we should manage separately these cases.
197 bool i2c_recv(void *_buf, size_t count)
199 uint8_t *buf = (uint8_t *)_buf;
205 if(!check_i2cStatus(I2C_EVENT_MASTER_BYTE_RECEIVED))
208 i2c->CR1 &= CR1_ACK_RESET;
215 i2c->CR1 &= CR1_ACK_RESET;
219 i2c->CR1 |= CR1_STOP_SET;
240 * Initialize I2C module.
242 void i2c_builtin_init(void)
246 RCC->APB2ENR |= RCC_APB2_GPIOB;
247 RCC->APB1ENR |= RCC_APB1_I2C1;
249 /* Set gpio to use I2C driver */
250 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SCL_PIN,
251 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
253 stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SDA_PIN,
254 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
257 /* Clear all needed registers */
264 /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
265 i2c->CR2 |= CR2_FREQ_36MHZ;
267 /* Configure spi in standard mode */
268 #if CONFIG_I2C_FREQ <= 100000
269 i2c->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (CONFIG_I2C_FREQ << 1));
270 i2c->TRISE |= (CR2_FREQ_36MHZ + 1);
272 #error fast mode not supported