bertos/cpu/cortex-m3/drv/i2c_stm32.c

   1 /**
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  20  * As a special exception, you may use this file as part of a free software
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  24  * file does not by itself cause the resulting executable to be covered by
  25  * the GNU General Public License.  This exception does not however
  26  * invalidate any other reasons why the executable file might be covered by
  27  * the GNU General Public License.
  28  *
  29  * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
  30  *
  31  * -->
  32  *
  33  * \brief STM32F103xx I2C driver.
  34  *
  35  * \author Daniele Basile <asterix@develer.com>
  36  */
  37
  38 #include "cfg/cfg_i2c.h"
  39
  40 #define LOG_LEVEL  I2C_LOG_LEVEL
  41 #define LOG_FORMAT I2C_LOG_FORMAT
  42 #include <cfg/log.h>
  43
  44 #include <cfg/debug.h>
  45 #include <cfg/macros.h> // BV()
  46 #include <cfg/module.h>
  47
  48 #include <drv/gpio_stm32.h>
  49 #include <drv/irq_cm3.h>
  50 #include <drv/clock_stm32.h>
  51 #include <drv/i2c.h>
  52 #include <drv/timer.h>
  53
  54 #include <io/stm32.h>
  55
  56
  57 struct I2cHardware
  58 {
  59         struct stm32_i2c *base;
  60         uint32_t clk_gpio_en;
  61         uint32_t clk_i2c_en;
  62         struct stm32_gpio *gpio_base;
  63         uint32_t pin_mask;
  64         uint8_t cache[2];
  65         bool cached;
  66 };
  67
  68 #define WAIT_BTF(base)        while( !(base->SR1 & BV(SR1_BTF)) )
  69 #define WAIT_RXNE(base)        while( !(base->SR1 & BV(SR1_RXNE)) )
  70
  71 INLINE uint32_t get_status(struct stm32_i2c *base)
  72 {
  73         return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
  74 }
  75
  76
  77 INLINE bool check_i2cStatus(I2c *i2c, uint32_t event)
  78 {
  79         while (true)
  80         {
  81                 uint32_t stat = get_status(i2c->hw->base);
  82
  83                 if (stat == event)
  84                         break;
  85
  86                 if (stat & SR1_ERR_MASK)
  87                 {
  88                         i2c->hw->base->SR1 &= ~SR1_ERR_MASK;
  89                         i2c->hw->base->CR1 |= CR1_START_SET;
  90                         return false;
  91                 }
  92
  93         }
  94
  95         return true;
  96 }
  97
  98 /**
  99  * Send START condition on the bus.
 100  *
 101  * \return true on success, false otherwise.
 102  */
 103 INLINE bool i2c_hw_restart(I2c *i2c)
 104 {
 105
 106         i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_START_SET;
 107
 108         if(check_i2cStatus(i2c, I2C_EVENT_MASTER_MODE_SELECT))
 109                 return true;
 110
 111         return false;
 112 }
 113
 114 /**
 115  * Send STOP condition.
 116  */
 117 static void i2c_hw_stop(I2c *i2c)
 118 {
 119         i2c->hw->base->CR1 |= CR1_STOP_SET;
 120 }
 121
 122 static void i2c_stm32_start(struct I2c *i2c, uint16_t slave_addr)
 123 {
 124         i2c->hw->cached = false;
 125
 126         if (I2C_TEST_START(i2c->flags) == I2C_START_W)
 127         {
 128                 /*
 129                  * Loop on the select write sequence: when the eeprom is busy
 130                  * writing previously sent data it will reply to the SLA_W
 131                  * control byte with a NACK.  In this case, we must
 132                  * keep trying until the eeprom responds with an ACK.
 133                  */
 134                 ticks_t start = timer_clock();
 135                 while (i2c_hw_restart(i2c))
 136                 {
 137                         i2c->hw->base->DR = slave_addr & OAR1_ADD0_RESET;
 138
 139                         if(check_i2cStatus(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
 140                                 break;
 141
 142                         if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
 143                         {
 144                                 LOG_ERR("Timeout on I2C START\n");
 145                                 i2c->errors |= I2C_NO_ACK;
 146                                 i2c_hw_stop(i2c);
 147                                 break;
 148                         }
 149                 }
 150
 151         }
 152         else if (I2C_TEST_START(i2c->flags) == I2C_START_R)
 153         {
 154                 i2c->hw->base->CR1 |= CR1_START_SET;
 155
 156                 if(!check_i2cStatus(i2c, I2C_EVENT_MASTER_MODE_SELECT))
 157                 {
 158                         LOG_ERR("ARBIT lost\n");
 159                         i2c->errors |= I2C_ARB_LOST;
 160                         i2c_hw_stop(i2c);
 161                         return;
 162                 }
 163
 164                 i2c->hw->base->DR = (slave_addr | OAR1_ADD0_SET);
 165
 166                 if (i2c->xfer_size == 2)
 167                         i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_POS_SET;
 168
 169                 if(!check_i2cStatus(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
 170                 {
 171                         LOG_ERR("SLAR NACK:%08lx\n", get_status(i2c->hw->base));
 172                         i2c->errors |= I2C_NO_ACK;
 173                         i2c_hw_stop(i2c);
 174                         return;
 175                 }
 176
 177
 178                 if (i2c->xfer_size == 1)
 179                 {
 180                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 181
 182                         cpu_flags_t irq;
 183                         IRQ_SAVE_DISABLE(irq);
 184
 185                         (void)i2c->hw->base->SR2;
 186
 187                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 188                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 189
 190                         IRQ_RESTORE(irq);
 191
 192                         WAIT_RXNE(i2c->hw->base);
 193
 194                         i2c->hw->cache[0] = i2c->hw->base->DR;
 195                         i2c->hw->cached = true;
 196
 197                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 198                                 while (i2c->hw->base->CR1 & CR1_STOP_SET);
 199
 200                         i2c->hw->base->CR1 |= CR1_ACK_SET;
 201
 202                 }
 203                 else if (i2c->xfer_size == 2)
 204                 {
 205                         cpu_flags_t irq;
 206                         IRQ_SAVE_DISABLE(irq);
 207
 208                         (void)i2c->hw->base->SR2;
 209
 210                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 211
 212                         IRQ_RESTORE(irq);
 213
 214                         WAIT_BTF(i2c->hw->base);
 215
 216                         IRQ_SAVE_DISABLE(irq);
 217
 218                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 219                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 220
 221                         /*
 222                          * We store read bytes like a fifo..
 223                          */
 224                         i2c->hw->cache[1] = i2c->hw->base->DR;
 225                         i2c->hw->cache[0] = i2c->hw->base->DR;
 226                         i2c->hw->cached = true;
 227
 228                         IRQ_RESTORE(irq);
 229
 230                         i2c->hw->base->CR1 &= CR1_POS_RESET;
 231                         i2c->hw->base->CR1 |= CR1_ACK_SET;
 232                 }
 233         }
 234         else
 235         {
 236                 ASSERT(0);
 237         }
 238
 239 }
 240
 241 static void i2c_stm32_put(I2c *i2c, const uint8_t data)
 242 {
 243         i2c->hw->base->DR = data;
 244
 245         WAIT_BTF(i2c->hw->base);
 246
 247
 248         /* Generate the stop if we finish to send all programmed bytes */
 249         if ((i2c->xfer_size == 1) &&(I2C_TEST_STOP(i2c->flags) == I2C_STOP))
 250         {
 251                         check_i2cStatus(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED);
 252                         i2c_hw_stop(i2c);
 253         }
 254 }
 255
 256 static uint8_t i2c_stm32_get(I2c *i2c)
 257 {
 258         if (i2c->hw->cached)
 259         {
 260                 ASSERT(i2c->xfer_size <= 2);
 261                 return i2c->hw->cache[i2c->xfer_size - 1];
 262         }
 263         else
 264         {
 265                 WAIT_BTF(i2c->hw->base);
 266
 267                 if (i2c->xfer_size == 3)
 268                 {
 269                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 270
 271                         cpu_flags_t irq;
 272                         IRQ_SAVE_DISABLE(irq);
 273
 274                         uint8_t data = i2c->hw->base->DR;
 275
 276                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 277                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 278
 279                         i2c->hw->cache[1] = i2c->hw->base->DR;
 280
 281                         IRQ_RESTORE(irq);
 282
 283                         WAIT_RXNE(i2c->hw->base);
 284
 285                         i2c->hw->cache[0] = i2c->hw->base->DR;
 286                         i2c->hw->cached = true;
 287
 288                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 289                                 while (i2c->hw->base->CR1 & CR1_STOP_SET);
 290
 291                         return data;
 292                 }
 293                 else
 294                         return i2c->hw->base->DR;
 295         }
 296 }
 297
 298
 299 static const I2cVT i2c_stm32_vt =
 300 {
 301         .start = i2c_stm32_start,
 302         .get = i2c_stm32_get,
 303         .put = i2c_stm32_put,
 304         .send = i2c_swSend,
 305         .recv = i2c_swRecv,
 306 };
 307
 308 struct I2cHardware i2c_stm32_hw[] =
 309 {
 310         { /* I2C1 */
 311                 .base = (struct stm32_i2c *)I2C1_BASE,
 312                 .clk_gpio_en = RCC_APB2_GPIOB,
 313                 .clk_i2c_en  = RCC_APB1_I2C1,
 314                 .gpio_base = (struct stm32_gpio *)GPIOB_BASE,
 315                 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
 316         },
 317         #if 0
 318         { /* I2C2 */
 319                 .base = (struct stm32_i2c *)I2C2_BASE,
 320                 .clk_gpio_en = RCC_APB2_GPIO--,
 321                 .clk_i2c_en  = RCC_APB1_I2C2,
 322                 .gpio_base = (struct stm32_gpio *)GPIO---_BASE,
 323                 .pin_mask = (GPIO_I2C2_SCL_PIN | GPIO_I2C2_SDA_PIN),
 324         },
 325         #endif
 326 };
 327
 328 MOD_DEFINE(i2c);
 329
 330 /**
 331  * Initialize I2C module.
 332  */
 333 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
 334 {
 335
 336         i2c->hw = &i2c_stm32_hw[dev];
 337         i2c->vt = &i2c_stm32_vt;
 338
 339         RCC->APB2ENR |= i2c->hw->clk_gpio_en;
 340         RCC->APB1ENR |= i2c->hw->clk_i2c_en;
 341
 342         /* Set gpio to use I2C driver */
 343         stm32_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask,
 344                                 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
 345
 346         /* Clear all needed registers */
 347         i2c->hw->base->CR1 = 0;
 348         i2c->hw->base->CR2 = 0;
 349         i2c->hw->base->CCR = 0;
 350         i2c->hw->base->TRISE = 0;
 351         i2c->hw->base->OAR1 = 0;
 352
 353         /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
 354         i2c->hw->base->CR2 |= CR2_FREQ_36MHZ;
 355
 356         /* Configure spi in standard mode */
 357         ASSERT2(clock >= 100000, "fast mode not supported");
 358
 359         i2c->hw->base->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (clock << 1));
 360         i2c->hw->base->TRISE |= (CR2_FREQ_36MHZ + 1);
 361
 362         i2c->hw->base->CR1 |= CR1_PE_SET;
 363
 364         MOD_INIT(i2c);
 365 }