bertos/cpu/cortex-m3/drv/i2c_stm32.c

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  27  * the GNU General Public License.
  28  *
  29  * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
  30  *
  31  * -->
  32  *
  33  * \brief STM32F103xx I2C driver.
  34  *
  35  * \author Daniele Basile <asterix@develer.com>
  36  */
  37
  38 #include "cfg/cfg_i2c.h"
  39
  40 #define LOG_LEVEL  I2C_LOG_LEVEL
  41 #define LOG_FORMAT I2C_LOG_FORMAT
  42 #include <cfg/log.h>
  43
  44 #include <cfg/debug.h>
  45 #include <cfg/macros.h> // BV()
  46 #include <cfg/module.h>
  47
  48 #include <cpu/power.h>
  49 #include <drv/gpio_stm32.h>
  50 #include <drv/irq_cm3.h>
  51 #include <drv/clock_stm32.h>
  52 #include <drv/i2c.h>
  53 #include <drv/timer.h>
  54
  55 #include <io/stm32.h>
  56
  57
  58 struct I2cHardware
  59 {
  60         struct stm32_i2c *base;
  61         uint32_t clk_i2c_en;
  62         uint32_t pin_mask;
  63         uint8_t cache[2];
  64         bool cached;
  65 };
  66
  67 #define WAIT_BTF(base) \
  68         do { \
  69                 while (!(base->SR1 & BV(SR1_BTF))) \
  70                         cpu_relax(); \
  71         } while (0)
  72
  73 #define WAIT_RXNE(base) \
  74         do { \
  75                 while (!(base->SR1 & BV(SR1_RXNE))) \
  76                         cpu_relax(); \
  77         } while (0)
  78
  79 INLINE uint32_t get_status(struct stm32_i2c *base)
  80 {
  81         return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
  82 }
  83
  84
  85 INLINE bool wait_event(I2c *i2c, uint32_t event)
  86 {
  87         while (true)
  88         {
  89                 uint32_t stat = get_status(i2c->hw->base);
  90
  91                 if (stat == event)
  92                         break;
  93
  94                 if (stat & SR1_ERR_MASK)
  95                 {
  96                         i2c->hw->base->SR1 &= ~SR1_ERR_MASK;
  97                         return false;
  98                 }
  99                 cpu_relax();
 100         }
 101         return true;
 102 }
 103
 104 static void i2c_stm32_start(struct I2c *i2c, uint16_t slave_addr)
 105 {
 106         i2c->hw->cached = false;
 107
 108         if (I2C_TEST_START(i2c->flags) == I2C_START_W)
 109         {
 110                 /*
 111                  * Loop on the select write sequence: when the eeprom is busy
 112                  * writing previously sent data it will reply to the SLA_W
 113                  * control byte with a NACK.  In this case, we must
 114                  * keep trying until the eeprom responds with an ACK.
 115                  */
 116                 ticks_t start = timer_clock();
 117                 while (true)
 118                 {
 119                         i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_START_SET;
 120
 121                         if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
 122                         {
 123                                 LOG_ERR("ARBIT lost\n");
 124                                 i2c->errors |= I2C_ARB_LOST;
 125                                 break;
 126                         }
 127
 128                         i2c->hw->base->DR = slave_addr & OAR1_ADD0_RESET;
 129
 130                         if(wait_event(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
 131                                 break;
 132
 133                         if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
 134                         {
 135                                 LOG_ERR("Timeout on I2C START\n");
 136                                 i2c->errors |= I2C_START_TIMEOUT;
 137                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 138                                 break;
 139                         }
 140                 }
 141
 142         }
 143         else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
 144         {
 145                 i2c->hw->base->CR1 |= CR1_START_SET;
 146
 147                 if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
 148                 {
 149                         LOG_ERR("ARBIT lost\n");
 150                         i2c->errors |= I2C_ARB_LOST;
 151                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 152                         return;
 153                 }
 154
 155                 i2c->hw->base->DR = (slave_addr | OAR1_ADD0_SET);
 156
 157                 if (i2c->xfer_size == 2)
 158                         i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_POS_SET;
 159
 160                 if(!wait_event(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
 161                 {
 162                         LOG_ERR("SLAR NACK:%08lx\n", get_status(i2c->hw->base));
 163                         i2c->errors |= I2C_NO_ACK;
 164                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 165                         return;
 166                 }
 167
 168                 if (i2c->xfer_size == 1)
 169                 {
 170                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 171
 172                         cpu_flags_t irq;
 173                         IRQ_SAVE_DISABLE(irq);
 174
 175                         (void)i2c->hw->base->SR2;
 176
 177                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 178                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 179
 180                         IRQ_RESTORE(irq);
 181
 182                         WAIT_RXNE(i2c->hw->base);
 183
 184                         i2c->hw->cache[0] = i2c->hw->base->DR;
 185                         i2c->hw->cached = true;
 186
 187                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 188                                 while (i2c->hw->base->CR1 & CR1_STOP_SET);
 189
 190                         i2c->hw->base->CR1 |= CR1_ACK_SET;
 191
 192                 }
 193                 else if (i2c->xfer_size == 2)
 194                 {
 195                         cpu_flags_t irq;
 196                         IRQ_SAVE_DISABLE(irq);
 197
 198                         (void)i2c->hw->base->SR2;
 199
 200                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 201
 202                         IRQ_RESTORE(irq);
 203
 204                         WAIT_BTF(i2c->hw->base);
 205
 206                         IRQ_SAVE_DISABLE(irq);
 207
 208                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 209                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 210
 211                         /*
 212                          * We store read bytes like a fifo..
 213                          */
 214                         i2c->hw->cache[1] = i2c->hw->base->DR;
 215                         i2c->hw->cache[0] = i2c->hw->base->DR;
 216                         i2c->hw->cached = true;
 217
 218                         IRQ_RESTORE(irq);
 219
 220                         i2c->hw->base->CR1 &= CR1_POS_RESET;
 221                         i2c->hw->base->CR1 |= CR1_ACK_SET;
 222                 }
 223         }
 224 }
 225
 226 static void i2c_stm32_put(I2c *i2c, const uint8_t data)
 227 {
 228         i2c->hw->base->DR = data;
 229
 230         WAIT_BTF(i2c->hw->base);
 231
 232         /* Generate the stop if we finish to send all programmed bytes */
 233         if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
 234         {
 235                         wait_event(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED);
 236                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 237         }
 238 }
 239
 240 static uint8_t i2c_stm32_get(I2c *i2c)
 241 {
 242         if (i2c->hw->cached)
 243         {
 244                 ASSERT(i2c->xfer_size <= 2);
 245                 return i2c->hw->cache[i2c->xfer_size - 1];
 246         }
 247         else
 248         {
 249                 WAIT_BTF(i2c->hw->base);
 250
 251                 if (i2c->xfer_size == 3)
 252                 {
 253                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 254
 255                         cpu_flags_t irq;
 256                         IRQ_SAVE_DISABLE(irq);
 257
 258                         uint8_t data = i2c->hw->base->DR;
 259
 260                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 261                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 262
 263                         i2c->hw->cache[1] = i2c->hw->base->DR;
 264
 265                         IRQ_RESTORE(irq);
 266
 267                         WAIT_RXNE(i2c->hw->base);
 268
 269                         i2c->hw->cache[0] = i2c->hw->base->DR;
 270                         i2c->hw->cached = true;
 271
 272                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 273                                 while (i2c->hw->base->CR1 & CR1_STOP_SET);
 274
 275                         return data;
 276                 }
 277                 else
 278                         return i2c->hw->base->DR;
 279         }
 280 }
 281
 282
 283 static const I2cVT i2c_stm32_vt =
 284 {
 285         .start = i2c_stm32_start,
 286         .get = i2c_stm32_get,
 287         .put = i2c_stm32_put,
 288         .send = i2c_swSend,
 289         .recv = i2c_swRecv,
 290 };
 291
 292 struct I2cHardware i2c_stm32_hw[] =
 293 {
 294         { /* I2C1 */
 295                 .base = (struct stm32_i2c *)I2C1_BASE,
 296                 .clk_i2c_en  = RCC_APB1_I2C1,
 297                 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
 298         },
 299         { /* I2C2 */
 300                 .base = (struct stm32_i2c *)I2C2_BASE,
 301                 .clk_i2c_en  = RCC_APB1_I2C2,
 302                 .pin_mask = (GPIO_I2C2_SCL_PIN | GPIO_I2C2_SDA_PIN),
 303         },
 304 };
 305
 306 MOD_DEFINE(i2c);
 307
 308 /**
 309  * Initialize I2C module.
 310  */
 311 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
 312 {
 313
 314         i2c->hw = &i2c_stm32_hw[dev];
 315         i2c->vt = &i2c_stm32_vt;
 316
 317         RCC->APB2ENR |= RCC_APB2_GPIOB;
 318         RCC->APB1ENR |= i2c->hw->clk_i2c_en;
 319
 320         /* Set gpio to use I2C driver */
 321         stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, i2c->hw->pin_mask,
 322                                 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
 323
 324         /* Clear all needed registers */
 325         i2c->hw->base->CR1 = 0;
 326         i2c->hw->base->CR2 = 0;
 327         i2c->hw->base->CCR = 0;
 328         i2c->hw->base->TRISE = 0;
 329         i2c->hw->base->OAR1 = 0;
 330
 331         /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
 332         i2c->hw->base->CR2 |= CR2_FREQ_36MHZ;
 333
 334         /* Configure spi in standard mode */
 335         ASSERT2(clock >= 100000, "fast mode not supported");
 336
 337         i2c->hw->base->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (clock << 1));
 338         i2c->hw->base->TRISE |= (CR2_FREQ_36MHZ + 1);
 339
 340         i2c->hw->base->CR1 |= CR1_PE_SET;
 341
 342         MOD_INIT(i2c);
 343 }