bertos/cpu/cortex-m3/drv/i2c_stm32.c

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  27  * the GNU General Public License.
  28  *
  29  * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
  30  *
  31  * -->
  32  *
  33  * \brief STM32F103xx I2C driver.
  34  *
  35  * \author Daniele Basile <asterix@develer.com>
  36  */
  37
  38 #include "cfg/cfg_i2c.h"
  39
  40 #define LOG_LEVEL  I2C_LOG_LEVEL
  41 #define LOG_FORMAT I2C_LOG_FORMAT
  42 #include <cfg/log.h>
  43
  44 #include <cfg/debug.h>
  45 #include <cfg/macros.h> // BV()
  46 #include <cfg/module.h>
  47
  48 #include <cpu/power.h>
  49 #include <drv/gpio_stm32.h>
  50 #include <drv/irq_cm3.h>
  51 #include <drv/clock_stm32.h>
  52 #include <drv/i2c.h>
  53 #include <drv/timer.h>
  54
  55 #include <io/stm32.h>
  56
  57
  58 struct I2cHardware
  59 {
  60         struct stm32_i2c *base;
  61         uint32_t clk_i2c_en;
  62         uint32_t pin_mask;
  63         uint8_t cache[2];
  64         bool cached;
  65 };
  66
  67 #define WAIT_BTF(base) \
  68         do { \
  69                 while (!(base->SR1 & BV(SR1_BTF))) \
  70                         cpu_relax(); \
  71         } while (0)
  72
  73 #define WAIT_RXNE(base) \
  74         do { \
  75                 while (!(base->SR1 & BV(SR1_RXNE))) \
  76                         cpu_relax(); \
  77         } while (0)
  78
  79 INLINE uint32_t get_status(struct stm32_i2c *base)
  80 {
  81         return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
  82 }
  83
  84 /*
  85  * This fuction read the status registers of the i2c device
  86  * and waint until the selec event happen. If occur one error
  87  * the funtions return false.
  88  */
  89 INLINE bool wait_event(I2c *i2c, uint32_t event)
  90 {
  91         while (true)
  92         {
  93                 uint32_t stat = get_status(i2c->hw->base);
  94
  95                 if (stat == event)
  96                         break;
  97
  98                 if (stat & SR1_ERR_MASK)
  99                 {
 100                         i2c->hw->base->SR1 &= ~SR1_ERR_MASK;
 101                         return false;
 102                 }
 103                 cpu_relax();
 104         }
 105         return true;
 106 }
 107
 108
 109 INLINE void start_w(struct I2c *i2c, uint16_t slave_addr)
 110 {
 111         /*
 112          * Loop on the select write sequence: when the eeprom is busy
 113          * writing previously sent data it will reply to the SLA_W
 114          * control byte with a NACK.  In this case, we must
 115          * keep trying until the eeprom responds with an ACK.
 116          */
 117         ticks_t start = timer_clock();
 118         while (true)
 119         {
 120                 i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_START_SET;
 121
 122                 if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
 123                 {
 124                         LOG_ERR("ARBIT lost\n");
 125                         i2c->errors |= I2C_ARB_LOST;
 126                         break;
 127                 }
 128
 129                 i2c->hw->base->DR = slave_addr & OAR1_ADD0_RESET;
 130
 131                 if(wait_event(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
 132                         break;
 133
 134                 if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
 135                 {
 136                         LOG_ERR("Timeout on I2C START\n");
 137                         i2c->errors |= I2C_START_TIMEOUT;
 138                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 139                         break;
 140                 }
 141         }
 142 }
 143
 144 INLINE bool start_and_addr(struct I2c *i2c, uint16_t slave_addr)
 145 {
 146         i2c->hw->base->CR1 |= CR1_START_SET;
 147         if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
 148         {
 149                 LOG_ERR("ARBIT lost\n");
 150                 i2c->errors |= I2C_ARB_LOST;
 151                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 152                 return false;
 153         }
 154
 155         i2c->hw->base->DR = (slave_addr | OAR1_ADD0_SET);
 156
 157         if (i2c->xfer_size == 2)
 158                 i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_POS_SET;
 159
 160         if(!wait_event(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
 161         {
 162                 LOG_ERR("SLAR NACK:%08lx\n", get_status(i2c->hw->base));
 163                 i2c->errors |= I2C_NO_ACK;
 164                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 165                 return false;
 166         }
 167
 168         return true;
 169 }
 170
 171 INLINE void start_r(struct I2c *i2c, uint16_t slave_addr)
 172 {
 173         if (!start_and_addr(i2c, slave_addr))
 174                 return;
 175         /*
 176          * Due to the hardware receive bytes from slave in automatically mode
 177          * we should manage contextually all cases that we want to read one, two or more
 178          * than two bytes. To comply this behaviour to our api we shoul bufferd some byte
 179          * to hide all special case that needs to use this device.
 180          */
 181         if (i2c->xfer_size == 1)
 182         {
 183                 i2c->hw->base->CR1 &= CR1_ACK_RESET;
 184
 185                 cpu_flags_t irq;
 186
 187                 IRQ_SAVE_DISABLE(irq);
 188                 (void)i2c->hw->base->SR2;
 189                 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 190                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 191                 IRQ_RESTORE(irq);
 192
 193                 WAIT_RXNE(i2c->hw->base);
 194
 195                 i2c->hw->cache[0] = i2c->hw->base->DR;
 196                 i2c->hw->cached = true;
 197
 198                 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 199                         while (i2c->hw->base->CR1 & CR1_STOP_SET);
 200
 201                 i2c->hw->base->CR1 |= CR1_ACK_SET;
 202         }
 203         else if (i2c->xfer_size == 2)
 204         {
 205                 cpu_flags_t irq;
 206
 207                 IRQ_SAVE_DISABLE(irq);
 208                 (void)i2c->hw->base->SR2;
 209                 i2c->hw->base->CR1 &= CR1_ACK_RESET;
 210                 IRQ_RESTORE(irq);
 211
 212                 WAIT_BTF(i2c->hw->base);
 213
 214                 IRQ_SAVE_DISABLE(irq);
 215                 if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 216                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 217                 /*
 218                  * We store read bytes like a fifo..
 219                  */
 220                 i2c->hw->cache[1] = i2c->hw->base->DR;
 221                 i2c->hw->cache[0] = i2c->hw->base->DR;
 222                 i2c->hw->cached = true;
 223                 IRQ_RESTORE(irq);
 224
 225                 i2c->hw->base->CR1 &= CR1_POS_RESET;
 226                 i2c->hw->base->CR1 |= CR1_ACK_SET;
 227         }
 228 }
 229
 230 static void i2c_stm32_start(struct I2c *i2c, uint16_t slave_addr)
 231 {
 232         i2c->hw->cached = false;
 233
 234         if (I2C_TEST_START(i2c->flags) == I2C_START_W)
 235                 start_w(i2c, slave_addr);
 236         else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
 237                 start_r(i2c, slave_addr);
 238 }
 239
 240 static void i2c_stm32_putc(I2c *i2c, const uint8_t data)
 241 {
 242         i2c->hw->base->DR = data;
 243
 244         WAIT_BTF(i2c->hw->base);
 245
 246         /* Generate the stop if we finish to send all programmed bytes */
 247         if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
 248         {
 249                         wait_event(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED);
 250                         i2c->hw->base->CR1 |= CR1_STOP_SET;
 251         }
 252 }
 253
 254 static uint8_t i2c_stm32_getc(I2c *i2c)
 255 {
 256         if (i2c->hw->cached)
 257         {
 258                 ASSERT(i2c->xfer_size <= 2);
 259                 return i2c->hw->cache[i2c->xfer_size - 1];
 260         }
 261         else
 262         {
 263                 WAIT_BTF(i2c->hw->base);
 264
 265                 if (i2c->xfer_size == 3)
 266                 {
 267                         i2c->hw->base->CR1 &= CR1_ACK_RESET;
 268
 269                         cpu_flags_t irq;
 270                         IRQ_SAVE_DISABLE(irq);
 271
 272                         uint8_t data = i2c->hw->base->DR;
 273
 274                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 275                                 i2c->hw->base->CR1 |= CR1_STOP_SET;
 276
 277                         i2c->hw->cache[1] = i2c->hw->base->DR;
 278
 279                         IRQ_RESTORE(irq);
 280
 281                         WAIT_RXNE(i2c->hw->base);
 282
 283                         i2c->hw->cache[0] = i2c->hw->base->DR;
 284                         i2c->hw->cached = true;
 285
 286                         if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
 287                                 while (i2c->hw->base->CR1 & CR1_STOP_SET);
 288
 289                         return data;
 290                 }
 291                 else
 292                         return i2c->hw->base->DR;
 293         }
 294 }
 295
 296
 297 static const I2cVT i2c_stm32_vt =
 298 {
 299         .start = i2c_stm32_start,
 300         .getc = i2c_stm32_getc,
 301         .putc = i2c_stm32_putc,
 302         .write = i2c_genericWrite,
 303         .read = i2c_genericRead,
 304 };
 305
 306 static struct I2cHardware i2c_stm32_hw[] =
 307 {
 308         { /* I2C1 */
 309                 .base = (struct stm32_i2c *)I2C1_BASE,
 310                 .clk_i2c_en  = RCC_APB1_I2C1,
 311                 .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
 312         },
 313         { /* I2C2 */
 314                 .base = (struct stm32_i2c *)I2C2_BASE,
 315                 .clk_i2c_en  = RCC_APB1_I2C2,
 316                 .pin_mask = (GPIO_I2C2_SCL_PIN | GPIO_I2C2_SDA_PIN),
 317         },
 318 };
 319
 320 /**
 321  * Initialize I2C module.
 322  */
 323 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
 324 {
 325
 326         i2c->hw = &i2c_stm32_hw[dev];
 327         i2c->vt = &i2c_stm32_vt;
 328
 329         RCC->APB2ENR |= RCC_APB2_GPIOB;
 330         RCC->APB1ENR |= i2c->hw->clk_i2c_en;
 331
 332         /* Set gpio to use I2C driver */
 333         stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, i2c->hw->pin_mask,
 334                                 GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
 335
 336         /* Clear all needed registers */
 337         i2c->hw->base->CR1 = 0;
 338         i2c->hw->base->CR2 = 0;
 339         i2c->hw->base->CCR = 0;
 340         i2c->hw->base->TRISE = 0;
 341         i2c->hw->base->OAR1 = 0;
 342
 343         /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
 344         i2c->hw->base->CR2 |= CR2_FREQ_36MHZ;
 345
 346         /* Configure spi in standard mode */
 347         ASSERT2(clock >= 100000, "fast mode not supported");
 348
 349         i2c->hw->base->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (clock << 1));
 350         i2c->hw->base->TRISE |= (CR2_FREQ_36MHZ + 1);
 351
 352         i2c->hw->base->CR1 |= CR1_PE_SET;
 353 }