4 * This file is part of BeRTOS.
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
39 * TODO: Revise the public api of this module to be more generic. Evalutate to
40 * implement the more generic layer to be common to all I2S BeRTOS drivers.
43 #include "cfg/cfg_i2s.h"
45 // Define log settings for cfg/log.h.
46 #define LOG_LEVEL I2S_LOG_LEVEL
47 #define LOG_FORMAT I2S_LOG_FORMAT
50 #include <drv/timer.h>
51 #include <drv/irq_cm3.h>
59 #define DATALEN (15 & SSC_DATLEN_MASK)
60 #define BITS_PER_CHANNEL 16
61 #define N_OF_CHANNEL 2
62 // TODO: check the computed value?
63 /* The last parameter (2) is due to the hadware on at91sam7s. */
64 #define MCK_DIV (CPU_FREQ / (44100 * BITS_PER_CHANNEL * N_OF_CHANNEL* 2))
66 #define CONFIG_DELAY 0
67 #define CONFIG_PERIOD 15
68 #define CONFIG_DATNB 1
69 #define CONFIG_FSLEN 15
72 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
73 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
74 #define DATNB ((CONFIG_DATNB << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
75 #define FSLEN ((CONFIG_FSLEN << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
81 SSC_CR = BV(SSC_TXDIS);
89 SSC_CR = BV(SSC_TXEN);
95 static DECLARE_ISR(irq_ssc)
101 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
102 PIO_PERIPH_SEL(SSC_PORT, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
103 pmc_periphEnable(SSC_ID);
106 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
108 /* Set transmission clock */
109 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
110 /* Set the transmission mode:
111 * - the clk is generate from master clock
112 * - clock only during transfer
113 * - transmit Clock Gating Selection none
114 * - DELAY cycle insert before starting transmission
115 * - generate frame sync each 2*(PERIOD + 1) tramit clock
116 * - Receive start on falling edge RF
118 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
119 /* Set the transmission frame mode:
120 * - data len DATALEN + 1
121 * - word per frame DATNB + 1
122 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
123 * - DELAY cycle insert before starting transmission
125 * - Frame sync output selection negative
127 SSC_TFMR = DATALEN | DATNB | FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;