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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
39 #include "hw/hw_i2s.h"
41 #include "cfg/cfg_i2s.h"
43 // Define log settings for cfg/log.h.
44 #define LOG_LEVEL I2S_LOG_LEVEL
45 #define LOG_FORMAT I2S_LOG_FORMAT
48 #include <drv/timer.h>
50 #include <drv/dmac_sam3.h>
52 #include <mware/event.h>
66 struct I2sHardware i2s_hw;
67 static Event data_ready;
80 static int16_t *sample_buff;
81 static size_t next_idx = 0;
82 static size_t chunk_size = 0;
83 static size_t remaing_size = 0;
84 static size_t transfer_size = 0;
85 static bool single_transfer;
87 static void sam3_i2s_txStop(I2s *i2s)
90 SSC_CR = BV(SSC_TXDIS);
91 dmac_stop(I2S_DMAC_CH);
96 event_do(&data_ready);
99 static void sam3_i2s_txWait(I2s *i2s)
102 event_wait(&data_ready);
105 static void i2s_dmac_irq(uint32_t status)
110 single_transfer = false;
114 if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
117 // Disable to reset channel and clear fifo
118 DMAC_CHDR = BV(I2S_DMAC_CH);
126 curr->src_addr = (uint32_t)&sample_buff[next_idx];
127 curr->dst_addr = (uint32_t)&SSC_THR;
128 curr->dsc_addr = (uint32_t)next;
129 curr->ctrla = ctrla | (chunk_size & 0xffff);
130 curr->ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
132 remaing_size -= chunk_size;
133 next_idx += chunk_size;
135 if (remaing_size <= 0)
137 remaing_size = transfer_size;
142 event_do(&data_ready);
146 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
149 ASSERT(len >= slice_len);
150 ASSERT(!(len % slice_len));
152 i2s->hw->end = false;
153 single_transfer = false;
155 sample_buff = (int16_t *)buf;
157 chunk_size = slice_len / 2;
158 remaing_size = len / 2;
159 transfer_size = len / 2;
163 DMAC_CHDR = BV(I2S_DMAC_CH);
164 reg32_t reg = DMAC_EBCISR;
166 LOG_INFO("Start streaming [%08lx]\n", reg);
168 cfg = BV(DMAC_CFG_DST_H2SEL) | BV(DMAC_CFG_SOD) |
169 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
170 ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
171 ctrlb = DMAC_CTRLB_FC_MEM2PER_DMA_FC | DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
177 i2s->ctx.tx_callback(i2s, &sample_buff[0], chunk_size * 2);
179 lli0.src_addr = (uint32_t)&sample_buff[0];
180 lli0.dst_addr = (uint32_t)&SSC_THR;
181 lli0.dsc_addr = (uint32_t)next;
182 lli0.ctrla = ctrla | (chunk_size & 0xffff);
183 lli0.ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
185 remaing_size -= chunk_size;
186 next_idx += chunk_size;
188 if (chunk_size <= remaing_size)
190 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
196 lli1.src_addr = (uint32_t)&sample_buff[next_idx];
197 lli1.dst_addr = (uint32_t)&SSC_THR;
198 lli1.dsc_addr = (uint32_t)next;
199 lli1.ctrla = ctrla | (chunk_size & 0xffff);
200 lli1.ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
202 remaing_size -= chunk_size;
203 next_idx += chunk_size;
206 dmac_setLLITransfer(I2S_DMAC_CH, &lli0, cfg);
208 if (dmac_start(I2S_DMAC_CH) < 0)
210 LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
215 SSC_CR = BV(SSC_TXEN);
220 event_wait(&data_ready);
223 LOG_ERR("Errow while streaming.\n");
230 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
235 static void sam3_i2s_rxStop(I2s *i2s)
238 SSC_CR = BV(SSC_TXDIS);
241 static void sam3_i2s_rxWait(I2s *i2s)
246 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
255 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
261 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
267 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
271 single_transfer = true;
273 uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
274 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
275 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
276 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
277 DMAC_CTRLB_FC_MEM2PER_DMA_FC |
278 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
280 dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
281 dmac_configureDmac(I2S_DMAC_CH, len, cfg, ctrla, ctrlb);
282 dmac_start(I2S_DMAC_CH);
284 SSC_CR = BV(SSC_TXEN);
287 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
291 uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL) |
292 ((4 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (4 & DMAC_CFG_SRC_PER_MASK);
293 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
294 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
295 DMAC_CTRLB_FC_PER2MEM_DMA_FC |
296 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
298 dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
299 dmac_configureDmac(I2S_DMAC_CH, len / 2, cfg, ctrla, ctrlb);
300 dmac_start(I2S_DMAC_CH);
302 SSC_CR = BV(SSC_RXEN);
305 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
309 SSC_CR = BV(SSC_TXEN);
310 while(!(SSC_SR & BV(SSC_TXRDY)))
317 static uint32_t sam3_i2s_read(struct I2s *i2s)
321 SSC_CR = BV(SSC_RXEN);
322 while(!(SSC_SR & BV(SSC_RXRDY)))
329 /* We divite for 2 because the min clock for i2s i MCLK/2 */
330 #define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
331 #define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
332 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
333 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
334 #define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
335 #define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
336 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
338 void i2s_init(I2s *i2s, int channel)
341 i2s->ctx.write = sam3_i2s_write;
342 i2s->ctx.tx_buf = sam3_i2s_txBuf;
343 i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
344 i2s->ctx.tx_start = sam3_i2s_txStart;
345 i2s->ctx.tx_wait = sam3_i2s_txWait;
346 i2s->ctx.tx_stop = sam3_i2s_txStop;
348 i2s->ctx.read = sam3_i2s_read;
349 i2s->ctx.rx_buf = sam3_i2s_rxBuf;
350 i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
351 i2s->ctx.rx_start = sam3_i2s_rxStart;
352 i2s->ctx.rx_wait = sam3_i2s_rxWait;
353 i2s->ctx.rx_stop = sam3_i2s_rxStop;
355 DB(i2s->ctx._type = I2S_SAM3X;)
360 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
361 PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
362 PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
363 PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
366 pmc_periphEnable(SSC_ID);
369 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
371 /* Set transmission clock */
372 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
373 /* Set the transmission mode:
374 * - the clk is generate from master clock
375 * - clock only during transfer
376 * - transmit Clock Gating Selection none
377 * - DELAY cycle insert before starting transmission
378 * - generate frame sync each 2*(PERIOD + 1) tramit clock
379 * - Receive start on falling edge RF
381 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
382 /* Set the transmission frame mode:
383 * - data len DATALEN + 1
384 * - word per frame DATNB + 1
385 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
386 * - DELAY cycle insert before starting transmission
388 * - Frame sync output selection negative
390 SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
393 // Receiver should start on TX and take the clock from TK
394 SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
395 SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
398 SSC_IDR = 0xFFFFFFFF;
400 dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq);
401 event_initGeneric(&data_ready);