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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2s.h"
40 // Define log settings for cfg/log.h.
41 #define LOG_LEVEL I2S_LOG_LEVEL
42 #define LOG_FORMAT I2S_LOG_FORMAT
45 #include <drv/timer.h>
47 #include <drv/dmac_sam3.h>
49 #include <mware/event.h>
63 struct I2sHardware i2s_hw;
64 static Event data_ready;
72 static int16_t *sample_buff;
73 static size_t next_idx = 0;
74 static size_t chunk_size = 0;
75 static size_t remaing_size = 0;
76 static size_t transfer_size = 0;
77 static bool single_transfer;
79 static void sam3_i2s_txStop(I2s *i2s)
82 SSC_CR = BV(SSC_TXDIS);
83 dmac_stop(I2S_DMAC_CH);
88 event_do(&data_ready);
91 static void sam3_i2s_txWait(I2s *i2s)
94 event_wait(&data_ready);
103 static void i2s_dmac_irq(uint32_t status)
108 single_transfer = false;
112 if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
115 DMAC_CHDR = BV(I2S_DMAC_CH);
116 kprintf("irq_err[%08lx]\n", DMAC_EBCISR);
124 curr->src_addr = (uint32_t)&sample_buff[next_idx];
125 curr->dst_addr = (uint32_t)&SSC_THR;
126 curr->dsc_addr = (uint32_t)next;
127 curr->ctrla = ctrla | (chunk_size & 0xffff);
128 curr->ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
130 remaing_size -= chunk_size;
131 next_idx += chunk_size;
133 if (remaing_size <= 0)
135 remaing_size = transfer_size;
141 event_do(&data_ready);
145 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
148 ASSERT(len >= slice_len);
149 ASSERT(!(len % slice_len));
151 i2s->hw->end = false;
152 single_transfer = false;
154 sample_buff = (int16_t *)buf;
156 chunk_size = slice_len / 2;
157 remaing_size = len / 2;
158 transfer_size = len / 2;
163 DMAC_CHDR = BV(I2S_DMAC_CH);
164 kprintf("Start streaming [%08lx]\n", DMAC_EBCISR);
166 cfg = BV(DMAC_CFG_DST_H2SEL) | BV(DMAC_CFG_SOD) |
167 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
169 ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD |
170 DMAC_CTRLA_DST_WIDTH_HALF_WORD;
172 ctrlb = DMAC_CTRLB_FC_MEM2PER_DMA_FC |
173 DMAC_CTRLB_DST_INCR_FIXED |
174 DMAC_CTRLB_SRC_INCR_INCREMENTING;
180 i2s->ctx.tx_callback(i2s, &sample_buff[0], chunk_size * 2);
182 lli0.src_addr = (uint32_t)&sample_buff[0];
183 lli0.dst_addr = (uint32_t)&SSC_THR;
184 lli0.dsc_addr = (uint32_t)next;
185 lli0.ctrla = ctrla | (chunk_size & 0xffff) ;
186 lli0.ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
188 remaing_size -= chunk_size;
189 next_idx += chunk_size;
191 if (chunk_size <= remaing_size)
193 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
199 lli1.src_addr = (uint32_t)&sample_buff[next_idx];
200 lli1.dst_addr = (uint32_t)&SSC_THR;
201 lli1.dsc_addr = (uint32_t)next;
202 lli1.ctrla = ctrla | (chunk_size & 0xffff);
203 lli1.ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
205 remaing_size -= chunk_size;
206 next_idx += chunk_size;
209 dmac_configureDmaCfgLLI(I2S_DMAC_CH, &lli0, cfg);
211 if (dmac_start(I2S_DMAC_CH) < 0)
212 kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
215 SSC_CR = BV(SSC_TXEN);
220 event_wait(&data_ready);
230 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
235 static void sam3_i2s_rxStop(I2s *i2s)
238 SSC_CR = BV(SSC_TXDIS);
241 static void sam3_i2s_rxWait(I2s *i2s)
246 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
255 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
261 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
264 return dmac_isDone(I2S_DMAC_CH);
267 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
271 single_transfer = true;
273 uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
274 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
275 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
276 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
277 DMAC_CTRLB_FC_MEM2PER_DMA_FC |
278 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
280 dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
281 dmac_configureDmac(I2S_DMAC_CH, len, cfg, ctrla, ctrlb);
282 dmac_start(I2S_DMAC_CH);
284 SSC_CR = BV(SSC_TXEN);
287 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
291 uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL) |
292 ((4 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (4 & DMAC_CFG_SRC_PER_MASK);
293 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
294 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
295 DMAC_CTRLB_FC_PER2MEM_DMA_FC |
296 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
298 dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
299 dmac_configureDmac(I2S_DMAC_CH, len / 2, cfg, ctrla, ctrlb);
300 dmac_start(I2S_DMAC_CH);
302 SSC_CR = BV(SSC_RXEN);
305 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
308 SSC_CR = BV(SSC_TXEN);
309 while(!(SSC_SR & BV(SSC_TXRDY)));
314 static uint32_t sam3_i2s_read(struct I2s *i2s)
317 SSC_CR = BV(SSC_RXEN);
318 while(!(SSC_SR & BV(SSC_RXRDY)));
323 static DECLARE_ISR(irq_ssc)
330 /* We divite for 2 because the min clock for i2s i MCLK/2 */
331 #define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
332 #define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
333 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
334 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
335 #define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
336 #define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
337 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
339 void i2s_init(I2s *i2s, int channel)
342 i2s->ctx.write = sam3_i2s_write;
343 i2s->ctx.tx_buf = sam3_i2s_txBuf;
344 i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
345 i2s->ctx.tx_start = sam3_i2s_txStart;
346 i2s->ctx.tx_wait = sam3_i2s_txWait;
347 i2s->ctx.tx_stop = sam3_i2s_txStop;
349 i2s->ctx.read = sam3_i2s_read;
350 i2s->ctx.rx_buf = sam3_i2s_rxBuf;
351 i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
352 i2s->ctx.rx_start = sam3_i2s_rxStart;
353 i2s->ctx.rx_wait = sam3_i2s_rxWait;
354 i2s->ctx.rx_stop = sam3_i2s_rxStop;
356 DB(i2s->ctx._type = I2S_SAM3X;)
359 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
360 PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
361 PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
362 PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
365 pmc_periphEnable(SSC_ID);
368 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
370 /* Set transmission clock */
371 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
372 /* Set the transmission mode:
373 * - the clk is generate from master clock
374 * - clock only during transfer
375 * - transmit Clock Gating Selection none
376 * - DELAY cycle insert before starting transmission
377 * - generate frame sync each 2*(PERIOD + 1) tramit clock
378 * - Receive start on falling edge RF
380 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
381 /* Set the transmission frame mode:
382 * - data len DATALEN + 1
383 * - word per frame DATNB + 1
384 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
385 * - DELAY cycle insert before starting transmission
387 * - Frame sync output selection negative
389 SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
392 // Receiver should start on TX and take the clock from TK
393 SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
394 SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
397 SSC_IDR = 0xFFFFFFFF;
399 dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq);
400 event_initGeneric(&data_ready);