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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2s.h"
40 // Define log settings for cfg/log.h.
41 #define LOG_LEVEL I2S_LOG_LEVEL
42 #define LOG_FORMAT I2S_LOG_FORMAT
45 #include <drv/timer.h>
47 #include <drv/dmac_sam3.h>
49 #include <mware/event.h>
63 struct I2sHardware i2s_hw;
64 static Event data_ready;
66 /* We divite for 2 because the min clock for i2s i MCLK/2 */
67 #define MCK_DIV (CPU_FREQ / (48000 * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
68 #define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
69 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
70 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
71 #define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
72 #define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
73 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
82 static uint8_t *sample_buff;
83 static size_t next_idx = 0;
84 static size_t chunk_size = 0;
85 static size_t remaing_size = 0;
88 static uint32_t ctrla;
89 static uint32_t ctrlb;
92 static void sam3_i2s_txStop(I2s *i2s)
95 SSC_CR = BV(SSC_TXDIS);
96 dmac_stop(I2S_DMAC_CH);
102 event_do(&data_ready);
105 static void sam3_i2s_txWait(I2s *i2s)
110 static void i2s_dmac_irq(void)
116 dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[next_idx], (uint32_t)&SSC_THR, (uint32_t)next);
117 dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
119 event_do(&data_ready);
122 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
125 ASSERT(len >= slice_len);
126 ASSERT(!(len % slice_len));
128 i2s->hw->end = false;
130 sample_buff = (uint8_t *)buf;
132 chunk_size = slice_len;
136 uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
137 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
138 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
139 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) |
140 DMAC_CTRLB_FC_MEM2PER_DMA_FC |
141 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
144 /* Program the dma with the first and second chunk of samples and update counter */
145 i2s->ctx.tx_callback(i2s, &sample_buff[0], chunk_size);
151 dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[0], (uint32_t)&SSC_THR,(uint32_t)next);
152 dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
154 remaing_size -= chunk_size;
155 next_idx += chunk_size;
157 if (chunk_size <= remaing_size)
159 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
165 dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[next_idx], (uint32_t)&SSC_THR,(uint32_t)next);
166 dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
168 remaing_size -= chunk_size;
169 next_idx += chunk_size;
172 if (dmac_start(I2S_DMAC_CH) < 0)
173 kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
175 SSC_CR = BV(SSC_TXEN);
179 event_wait(&data_ready);
183 remaing_size -= chunk_size;
184 next_idx += chunk_size;
186 if (remaing_size <= 0)
192 if (dmac_start(I2S_DMAC_CH) < 0)
193 kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
195 i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
199 static void sam3_i2s_rxStop(I2s *i2s)
202 SSC_CR = BV(SSC_TXDIS);
205 static void sam3_i2s_rxWait(I2s *i2s)
210 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
219 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
222 return i2s->hw->end;//dmac_isDone(&dmac);
225 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
228 return dmac_isDone(I2S_DMAC_CH);
231 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
235 uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
236 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
237 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
238 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
239 DMAC_CTRLB_FC_MEM2PER_DMA_FC |
240 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
242 dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
243 dmac_configureDmac(I2S_DMAC_CH, len / 2, cfg, ctrla, ctrlb);
244 dmac_start(I2S_DMAC_CH);
246 SSC_CR = BV(SSC_TXEN);
249 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
253 uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL) |
254 ((4 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (4 & DMAC_CFG_SRC_PER_MASK);
255 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
256 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
257 DMAC_CTRLB_FC_PER2MEM_DMA_FC |
258 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
260 dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
261 dmac_configureDmac(I2S_DMAC_CH, len / 2, cfg, ctrla, ctrlb);
262 dmac_start(I2S_DMAC_CH);
264 SSC_CR = BV(SSC_RXEN);
267 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
270 SSC_CR = BV(SSC_TXEN);
271 while(!(SSC_SR & BV(SSC_TXRDY)));
276 static uint32_t sam3_i2s_read(struct I2s *i2s)
279 SSC_CR = BV(SSC_RXEN);
280 while(!(SSC_SR & BV(SSC_RXRDY)));
285 static DECLARE_ISR(irq_ssc)
289 void i2s_init(I2s *i2s, int channel)
292 i2s->ctx.write = sam3_i2s_write;
293 i2s->ctx.tx_buf = sam3_i2s_txBuf;
294 i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
295 i2s->ctx.tx_start = sam3_i2s_txStart;
296 i2s->ctx.tx_wait = sam3_i2s_txWait;
297 i2s->ctx.tx_stop = sam3_i2s_txStop;
299 i2s->ctx.read = sam3_i2s_read;
300 i2s->ctx.rx_buf = sam3_i2s_rxBuf;
301 i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
302 i2s->ctx.rx_start = sam3_i2s_rxStart;
303 i2s->ctx.rx_wait = sam3_i2s_rxWait;
304 i2s->ctx.rx_stop = sam3_i2s_rxStop;
306 DB(i2s->ctx._type = I2S_SAM3X;)
309 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
310 PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
311 PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
312 PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
315 pmc_periphEnable(SSC_ID);
318 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
320 /* Set transmission clock */
321 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
322 /* Set the transmission mode:
323 * - the clk is generate from master clock
324 * - clock only during transfer
325 * - transmit Clock Gating Selection none
326 * - DELAY cycle insert before starting transmission
327 * - generate frame sync each 2*(PERIOD + 1) tramit clock
328 * - Receive start on falling edge RF
330 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
331 /* Set the transmission frame mode:
332 * - data len DATALEN + 1
333 * - word per frame DATNB + 1
334 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
335 * - DELAY cycle insert before starting transmission
337 * - Frame sync output selection negative
339 SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
342 // Receiver should start on TX and take the clock from TK
343 SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
344 SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
347 SSC_IDR = 0xFFFFFFFF;
348 SSC_CR = BV(SSC_TXDIS) | BV(SSC_RXDIS);
350 dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq);
351 event_initGeneric(&data_ready);