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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2s.h"
40 // Define log settings for cfg/log.h.
41 #define LOG_LEVEL I2S_LOG_LEVEL
42 #define LOG_FORMAT I2S_LOG_FORMAT
45 #include <drv/timer.h>
47 #include <drv/dmac_sam3.h>
57 struct I2sHardware i2s_hw;
60 /* We divite for 2 because the min clock for i2s i MCLK/2 */
61 #define MCK_DIV (CPU_FREQ / (48000 * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
62 #define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
63 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
64 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
65 #define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
66 #define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
67 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
70 static void sam3_i2s_txStop(I2s *i2s)
73 SSC_CR = BV(SSC_TXDIS);
76 static void sam3_i2s_txWait(I2s *i2s)
81 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
87 static void sam3_i2s_rxStop(I2s *i2s)
90 SSC_CR = BV(SSC_TXDIS);
93 static void sam3_i2s_rxWait(I2s *i2s)
98 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
107 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
110 return dmac_isDone(&dmac);
113 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
116 return dmac_isDone(&dmac);;
119 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
123 uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
124 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
125 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
126 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
127 DMAC_CTRLB_FC_MEM2PER_DMA_FC |
128 DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
130 dmac_setSources(&dmac, (uint32_t)buf, (uint32_t)&SSC_THR);
131 dmac_configureDmac(&dmac, len, cfg, ctrla, ctrlb);
134 SSC_CR = BV(SSC_TXEN);
137 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
141 uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL) |
142 ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
143 uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
144 uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
145 DMAC_CTRLB_FC_PER2MEM_DMA_FC |
146 DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
148 dmac_setSources(&dmac, (uint32_t)&SSC_RHR, (uint32_t)buf);
149 dmac_configureDmac(&dmac, len, cfg, ctrla, ctrlb);
152 SSC_CR = BV(SSC_RXEN);
155 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
158 while(!(SSC_SR & BV(SSC_TXRDY)));
163 static uint32_t sam3_i2s_read(struct I2s *i2s)
166 while(!(SSC_SR & BV(SSC_RXRDY)));
171 static DECLARE_ISR(irq_ssc)
175 void i2s_init(I2s *i2s, int channel)
178 i2s->ctx.write = sam3_i2s_write;
179 i2s->ctx.tx_buf = sam3_i2s_txBuf;
180 i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
181 i2s->ctx.tx_start = sam3_i2s_txStart;
182 i2s->ctx.tx_wait = sam3_i2s_txWait;
183 i2s->ctx.tx_stop = sam3_i2s_txStop;
185 i2s->ctx.read = sam3_i2s_read;
186 i2s->ctx.rx_buf = sam3_i2s_rxBuf;
187 i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
188 i2s->ctx.rx_start = sam3_i2s_rxStart;
189 i2s->ctx.rx_wait = sam3_i2s_rxWait;
190 i2s->ctx.rx_stop = sam3_i2s_rxStop;
192 DB(i2s->ctx._type = I2S_SAM3X;)
195 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
196 PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
197 PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
198 PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
201 pmc_periphEnable(SSC_ID);
204 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
206 /* Set transmission clock */
207 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
208 /* Set the transmission mode:
209 * - the clk is generate from master clock
210 * - clock only during transfer
211 * - transmit Clock Gating Selection none
212 * - DELAY cycle insert before starting transmission
213 * - generate frame sync each 2*(PERIOD + 1) tramit clock
214 * - Receive start on falling edge RF
216 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
217 /* Set the transmission frame mode:
218 * - data len DATALEN + 1
219 * - word per frame DATNB + 1
220 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
221 * - DELAY cycle insert before starting transmission
223 * - Frame sync output selection negative
225 SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
228 // Receiver should start on TX and take the clock from TK
229 SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
230 SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
233 SSC_IDR = 0xFFFFFFFF;
234 SSC_CR = BV(SSC_TXDIS) | BV(SSC_RXDIS);