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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
39 * TODO: Revise the public api of this module to be more generic. Evalutate to
40 * implement the more generic layer to be common to all I2S BeRTOS drivers.
43 #include "cfg/cfg_i2s.h"
45 // Define log settings for cfg/log.h.
46 #define LOG_LEVEL I2S_LOG_LEVEL
47 #define LOG_FORMAT I2S_LOG_FORMAT
50 #include <drv/timer.h>
51 #include <drv/irq_cm3.h>
57 #define DATALEN (15 & SSC_DATLEN_MASK)
58 // FIXME: this is not correct for 16 <= DATALEN < 24
59 #define PDC_DIV ((DATALEN / 8) + 1)
61 * PDC_DIV must be 1, 2 or 4, which are the bytes that are transferred
62 * each time the PDC reads from memory.
64 STATIC_ASSERT(PDC_DIV % 2 == 0);
65 #define PDC_COUNT (CONFIG_PLAY_BUF_LEN / PDC_DIV)
67 static uint8_t play_buf1[CONFIG_PLAY_BUF_LEN];
68 static uint8_t play_buf2[CONFIG_PLAY_BUF_LEN];
70 // the buffer in PDC next is play_buf2
71 volatile bool is_second_buf_next;
73 uint8_t *i2s_getBuffer(unsigned buf_num)
75 LOG_INFO("getBuffer start\n");
83 if (buf_num == I2S_SECOND_BUF)
85 else if (buf_num == I2S_FIRST_BUF)
91 uint8_t *i2s_getFreeBuffer(void)
93 // wait PDC transmission end
94 if (!(SSC_SR & BV(SSC_ENDTX)))
98 // the last time we got called, the second buffer was in PDC next
99 if (is_second_buf_next)
101 is_second_buf_next = false;
104 // the last time the first buffer was in PDC next
107 is_second_buf_next = true;
113 SSC_TNPR = (reg32_t) ret_buf;
114 SSC_TNCR = PDC_COUNT;
121 SSC_CR = BV(SSC_TXDIS);
127 /* Some time must pass between disabling and enabling again the transmission
128 * on SSC. A good empirical value seems >15 us. We try to avoid putting an
129 * explicit delay, instead we disable the transmitter when a sound finishes
130 * and hope that the delay has passed before we enter here again.
132 SSC_CR = BV(SSC_TXDIS);
135 SSC_PTCR = BV(PDC_PTCR_TXTDIS);
136 SSC_TPR = (reg32_t)play_buf1;
138 SSC_TNPR = (reg32_t)play_buf2;
139 SSC_TNCR = PDC_COUNT;
140 is_second_buf_next = true;
142 SSC_PTCR = BV(PDC_PTSR_TXTEN);
145 SSC_CR = BV(SSC_TXEN);
150 #define BITS_PER_CHANNEL 16
151 #define N_OF_CHANNEL 2
152 // TODO: check the computed value?
153 /* The last parameter (2) is due to the hadware on at91sam7s. */
154 #define MCK_DIV (CPU_FREQ / CONFIG_SAMPLE_FREQ / BITS_PER_CHANNEL / N_OF_CHANNEL / 2)
156 #define CONFIG_DELAY 1
157 #define CONFIG_PERIOD 15
158 #define CONFIG_DATNB 1
159 #define CONFIG_FSLEN 15
161 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
162 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
163 #define DATNB ((CONFIG_DATNB << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
164 #define FSLEN ((CONFIG_FSLEN << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
166 #define SSC_DMA_IRQ_PRIORITY 5
169 static DECLARE_ISR(irq_ssc)
175 SSC_PIO_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
176 PIO_PERIPH_SEL(SSC_PORT, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), SSC_TRAN_PERIPH);
179 SSC_CR = BV(SSC_SWRST);
181 /* Set transmission clock */
182 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
183 /* Set the transmission mode:
184 * - the clk is generate from master clock
185 * - clock only during transfer
186 * - transmit Clock Gating Selection none
187 * - DELAY cycle insert before starting transmission
188 * - generate frame sync each 2*(PERIOD + 1) tramit clock
189 * - Receive start on falling edge RF
191 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_TRAN | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
192 /* Set the transmission frame mode:
193 * - data len DATALEN + 1
194 * - word per frame DATNB + 1
195 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
196 * - DELAY cycle insert before starting transmission
198 * - Frame sync output selection negative
200 SSC_TFMR = DATALEN | DATNB | FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
202 SSC_IDR = 0xFFFFFFFF;
203 sysirq_setHandler(INT_SSC, irq_ssc);
205 /* Clock DAC peripheral */
206 pmc_periphEnable(SSC_ID);
209 SSC_CR = BV(SSC_TXEN);