4 * This file is part of BeRTOS.
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
32 * \brief I2S driver implementation.
34 * \author Daniele Basile <asterix@develer.com>
38 #include "cfg/cfg_i2s.h"
40 // Define log settings for cfg/log.h.
41 #define LOG_LEVEL I2S_LOG_LEVEL
42 #define LOG_FORMAT I2S_LOG_FORMAT
45 #include <drv/timer.h>
55 struct I2sHardware i2s_hw;
58 /* We divite for 2 because the min clock for i2s i MCLK/2 */
59 #define MCK_DIV (CPU_FREQ / (48000 * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
60 #define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
61 #define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
62 #define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
63 #define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
64 #define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
65 #define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
68 static void sam3_i2s_txStop(I2s *i2s)
71 SSC_CR = BV(SSC_TXDIS);
74 static void sam3_i2s_txWait(I2s *i2s)
79 static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
87 static void sam3_i2s_rxStop(I2s *i2s)
90 SSC_CR = BV(SSC_TXDIS);
93 static void sam3_i2s_rxWait(I2s *i2s)
98 static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
107 static bool sam3_i2s_isTxFinish(struct I2s *i2s)
113 static bool sam3_i2s_isRxFinish(struct I2s *i2s)
119 static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
126 static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
133 static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
136 while(!(SSC_SR & BV(SSC_TXRDY)));
143 static uint32_t sam3_i2s_read(struct I2s *i2s)
146 while(!(SSC_SR & BV(SSC_RXRDY)));
151 static DECLARE_ISR(irq_ssc)
155 void i2s_init(I2s *i2s, int channel)
158 i2s->ctx.write = sam3_i2s_write;
159 i2s->ctx.tx_buf = sam3_i2s_txBuf;
160 i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
161 i2s->ctx.tx_start = sam3_i2s_txStart;
162 i2s->ctx.tx_wait = sam3_i2s_txWait;
163 i2s->ctx.tx_stop = sam3_i2s_txStop;
165 i2s->ctx.read = sam3_i2s_read;
166 i2s->ctx.rx_buf = sam3_i2s_rxBuf;
167 i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
168 i2s->ctx.rx_start = sam3_i2s_rxStart;
169 i2s->ctx.rx_wait = sam3_i2s_rxWait;
170 i2s->ctx.rx_stop = sam3_i2s_rxStop;
172 DB(i2s->ctx._type = I2S_SAM3X;)
175 PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
176 PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
177 PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
178 PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
181 pmc_periphEnable(SSC_ID);
184 SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS);
186 /* Set transmission clock */
187 SSC_CMR = MCK_DIV & SSC_DIV_MASK;
188 /* Set the transmission mode:
189 * - the clk is generate from master clock
190 * - clock only during transfer
191 * - transmit Clock Gating Selection none
192 * - DELAY cycle insert before starting transmission
193 * - generate frame sync each 2*(PERIOD + 1) tramit clock
194 * - Receive start on falling edge RF
196 SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F;
197 /* Set the transmission frame mode:
198 * - data len DATALEN + 1
199 * - word per frame DATNB + 1
200 * - frame sync len FSLEN + (FSLEN_EXT * 16) + 1
201 * - DELAY cycle insert before starting transmission
203 * - Frame sync output selection negative
205 SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
208 // Receiver should start on TX and take the clock from TK
209 SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
210 SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
213 SSC_IDR = 0xFFFFFFFF;
214 SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);