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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief AT91SAM3 debug support (implementation).
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include <cfg/cfg_debug.h>
39 #include <cfg/macros.h> /* for BV() */
41 #include <io/sam3_ints.h>
42 #include <io/sam3_gpio.h>
43 #include <io/sam3_pmc.h>
44 #include <io/sam3_uart.h>
47 #if CONFIG_KDEBUG_PORT == 0
48 #define UART_BASE UART0_BASE
49 #define UART_INT INT_UART0
50 #define UART_GPIO_BASE GPIO_PORTA_BASE
51 #define UART_PINS (GPIO_UART0_RX_PIN | GPIO_UART0_TX_PIN)
52 #elif (CONFIG_KDEBUG_PORT == 1) && !defined(CPU_CM3_AT91SAM3U)
53 #define UART_BASE UART1_BASE
54 #define UART_INT INT_UART1
55 #define UART_GPIO_BASE GPIO_PORTB_BASE
56 #define UART_PINS (GPIO_UART1_RX_PIN | GPIO_UART1_TX_PIN)
58 #error "UART port not supported in this board"
61 // TODO: refactor serial simple functions and use them, see lm3s kdebug
62 #define KDBG_WAIT_READY() while (!(HWREG(UART_BASE + UART_SR) & UART_SR_TXRDY)) {}
63 #define KDBG_WAIT_TXDONE() while (!(HWREG(UART_BASE + UART_SR) & UART_SR_TXEMPTY)) {}
65 #define KDBG_WRITE_CHAR(c) do { HWREG(UART_BASE + UART_THR) = (c); } while(0)
67 /* Debug unit is used only for debug purposes so does not generate interrupts. */
68 #define KDBG_MASK_IRQ(old) do { (void)old; } while(0)
70 /* Debug unit is used only for debug purposes so does not generate interrupts. */
71 #define KDBG_RESTORE_IRQ(old) do { (void)old; } while(0)
73 typedef uint32_t kdbg_irqsave_t;
76 INLINE void kdbg_hw_init(void)
78 /* Disable PIO mode and set appropriate UART pins peripheral mode */
79 HWREG(UART_GPIO_BASE + GPIO_PDR) = UART_PINS;
80 HWREG(UART_GPIO_BASE + GPIO_ABCDSR1) &= ~UART_PINS;
81 HWREG(UART_GPIO_BASE + GPIO_ABCDSR2) &= ~UART_PINS;
83 /* Enable the peripheral clock */
84 PMC_PCER_R = UART_INT;
86 /* Reset and disable receiver & transmitter */
87 HWREG(UART_BASE + UART_CR) = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
89 /* Set mode: normal, no parity */
90 HWREG(UART_BASE + UART_MR) = UART_MR_PAR_NO;
93 HWREG(UART_BASE + UART_BRGR) = CPU_FREQ / CONFIG_KDEBUG_BAUDRATE / 16;
95 /* Enable receiver & transmitter */
96 HWREG(UART_BASE + UART_CR) = UART_CR_RXEN | UART_CR_TXEN;