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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief Micron MT29F serial NAND driver for SAM3's static memory controller.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "mt29f_sam3.h"
39 #include "cfg/cfg_mt29f.h"
41 // Define log settings for cfg/log.h
42 #define LOG_LEVEL CONFIG_MT29F_LOG_LEVEL
43 #define LOG_FORMAT CONFIG_MT29F_LOG_FORMAT
46 #include <cfg/macros.h>
50 #include <drv/timer.h>
51 #include <drv/mt29f.h>
53 #include <cpu/power.h> /* cpu_relax() */
54 #include <cpu/types.h>
56 #include <string.h> /* memcpy() */
58 // Timeout for NAND operations in ms
59 #define MT29F_TMOUT 100
61 // NAND flash status codes
62 #define MT29F_STATUS_READY BV(6)
63 #define MT29F_STATUS_ERROR BV(0)
65 // NAND flash commands
66 #define MT29F_CMD_READ_1 0x00
67 #define MT29F_CMD_READ_2 0x30
68 #define MT29F_CMD_COPYBACK_READ_1 0x00
69 #define MT29F_CMD_COPYBACK_READ_2 0x35
70 #define MT29F_CMD_COPYBACK_PROGRAM_1 0x85
71 #define MT29F_CMD_COPYBACK_PROGRAM_2 0x10
72 #define MT29F_CMD_RANDOM_OUT 0x05
73 #define MT29F_CMD_RANDOM_OUT_2 0xE0
74 #define MT29F_CMD_RANDOM_IN 0x85
75 #define MT29F_CMD_READID 0x90
76 #define MT29F_CMD_WRITE_1 0x80
77 #define MT29F_CMD_WRITE_2 0x10
78 #define MT29F_CMD_ERASE_1 0x60
79 #define MT29F_CMD_ERASE_2 0xD0
80 #define MT29F_CMD_STATUS 0x70
81 #define MT29F_CMD_RESET 0xFF
83 // Addresses for sending command, addresses and data bytes to flash
84 #define MT29F_CMD_ADDR 0x60400000
85 #define MT29F_ADDR_ADDR 0x60200000
86 #define MT29F_DATA_ADDR 0x60000000
90 * Translate flash page index plus a byte offset
91 * in the five address cycles format needed by NAND.
93 * Cycles in x8 mode as the MT29F2G08AAD
94 * CA = column addr, PA = page addr, BA = block addr
96 * Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
97 * -------------------------------------------------------
98 * First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
99 * Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
100 * Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
101 * Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
102 * Fifth LOW LOW LOW LOW LOW LOW LOW BA16
104 static void getAddrCycles(uint32_t page, uint16_t offset, uint32_t *cycle0, uint32_t *cycle1234)
106 ASSERT(offset < MT29F_PAGE_SIZE);
108 *cycle0 = offset & 0xff;
109 *cycle1234 = (page << 8) | ((offset >> 8) & 0xf);
111 LOG_INFO("mt29f addr: %lx %lx\n", *cycle1234, *cycle0);
115 INLINE bool nfcIsBusy(void)
117 return HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000;
120 INLINE bool isCmdDone(void)
122 return SMC_SR & SMC_SR_CMDDONE;
125 static bool waitReadyBusy(void)
127 time_t start = timer_clock();
129 while (!(SMC_SR & SMC_SR_RB_EDGE0))
132 if (timer_clock() - start > MT29F_TMOUT)
134 LOG_INFO("mt29f: R/B timeout\n");
143 * Wait for transfer to complete until timeout.
144 * If transfer completes return true, false in case of timeout.
146 static bool waitTransferComplete(void)
148 time_t start = timer_clock();
150 while (!(SMC_SR & SMC_SR_XFRDONE))
153 if (timer_clock() - start > MT29F_TMOUT)
155 LOG_INFO("mt29f: xfer complete timeout\n");
165 * Send command to NAND and wait for completion.
167 static void sendCommand(uint32_t cmd,
168 int num_cycles, uint32_t cycle0, uint32_t cycle1234)
177 cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd);
178 *cmd_addr = cycle1234;
180 while (!isCmdDone());
184 static bool isOperationComplete(void)
189 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
190 MT29F_CMD_STATUS << 2,
193 status = (uint8_t)HWREG(MT29F_DATA_ADDR);
194 return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR);
198 static void chipReset(void)
201 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
202 MT29F_CMD_RESET << 2,
210 * Erase the whole block containing given page.
212 int mt29f_blockErase(Mt29f *chip, uint32_t page)
217 getAddrCycles(page, 0, &cycle0, &cycle1234);
220 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 |
221 (MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2),
222 3, 0, cycle1234 >> 8);
226 if (!isOperationComplete())
228 LOG_ERR("mt29f: error erasing block\n");
229 chip->status |= MT29F_ERR_ERASE;
238 * Read Device ID and configuration codes.
240 bool mt29f_getDevId(Mt29f *chip, uint8_t dev_id[5])
243 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_ONE |
244 MT29F_CMD_READID << 2,
248 if (!waitTransferComplete())
250 LOG_ERR("mt29f: getDevId timeout\n");
251 chip->status |= MT29F_ERR_RD_TMOUT;
255 memcpy(dev_id, (void *)NFC_SRAM_BASE_ADDR, 5);
260 static bool checkEcc(void)
262 // TODO: implement it actually...
263 LOG_INFO("ECC_SR1: 0x%lx\n", SMC_ECC_SR1);
268 static bool mt29f_readPage(Mt29f *chip, uint32_t page, uint16_t offset)
273 LOG_INFO("mt29f_readPage: page 0x%lx off 0x%x\n", page, offset);
275 getAddrCycles(page, offset, &cycle0, &cycle1234);
278 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE | NFC_CMD_VCMD2 |
279 (MT29F_CMD_READ_2 << 10) | (MT29F_CMD_READ_1 << 2),
280 5, cycle0, cycle1234);
283 if (!waitTransferComplete())
285 LOG_ERR("mt29f: read timeout\n");
286 chip->status |= MT29F_ERR_RD_TMOUT;
295 * Read page data and ECC, checking for errors and fixing them if
298 bool mt29f_read(Mt29f *chip, uint32_t page, void *buf, uint16_t size)
300 ASSERT(size <= MT29F_DATA_SIZE);
302 if (!mt29f_readPage(chip, page, 0))
305 memcpy(buf, (void *)NFC_SRAM_BASE_ADDR, size);
314 * Write data in NFC SRAM buffer to a NAND page, starting at a given offset.
315 * Usually offset will be 0 to write data or MT29F_DATA_SIZE to write the spare
318 * According to datasheet to get ECC computed by hardware is sufficient
319 * to write the main area. But it seems that in that way the last ECC_PR
320 * register is not generated. The workaround is to write data and dummy (ff)
321 * spare data in one write, at this point the last ECC_PR is correct and
322 * ECC data can be written in the spare area with a second program operation.
324 static bool mt29f_writePage(Mt29f *chip, uint32_t page, uint16_t offset)
329 LOG_INFO("mt29f_writePage: page 0x%lx off 0x%x\n", page, offset);
331 getAddrCycles(page, offset, &cycle0, &cycle1234);
334 NFC_CMD_NFCCMD | NFC_CMD_NFCWR | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE |
335 MT29F_CMD_WRITE_1 << 2,
336 5, cycle0, cycle1234);
338 if (!waitTransferComplete())
340 LOG_ERR("mt29f: write timeout\n");
341 chip->status |= MT29F_ERR_WR_TMOUT;
346 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
347 MT29F_CMD_WRITE_2 << 2,
352 if (!isOperationComplete())
354 LOG_ERR("mt29f: error writing page\n");
355 chip->status |= MT29F_ERR_WRITE;
364 * Write data in a page.
366 static bool mt29f_writePageData(Mt29f *chip, uint32_t page, const void *buf, uint16_t size)
368 ASSERT(size <= MT29F_DATA_SIZE);
370 memset((void *)NFC_SRAM_BASE_ADDR, 0xff, MT29F_PAGE_SIZE);
371 memcpy((void *)NFC_SRAM_BASE_ADDR, buf, size);
373 return mt29f_writePage(chip, page, 0);
378 * Write the ECC for a page.
380 * ECC data are extracted from ECC_PRx registers and written
381 * in the page's spare area.
382 * For 2048 bytes pages and 1 ECC word each 256 bytes,
383 * 24 bytes of ECC data are stored.
385 static bool mt29f_writePageEcc(Mt29f *chip, uint32_t page)
388 uint32_t *buf = (uint32_t *)NFC_SRAM_BASE_ADDR;
390 memset((void *)NFC_SRAM_BASE_ADDR, 0xff, MT29F_SPARE_SIZE);
392 for (i = 0; i < MT29F_ECC_NWORDS; i++)
393 buf[i] = *((reg32_t *)(SMC_BASE + SMC_ECC_PR0_OFF) + i);
395 return mt29f_writePage(chip, page, MT29F_DATA_SIZE);
399 bool mt29f_write(Mt29f *chip, uint32_t page, const void *buf, uint16_t size)
402 mt29f_writePageData(chip, page, buf, size) &&
403 mt29f_writePageEcc(chip, page);
407 int mt29f_error(Mt29f *chip)
413 void mt29f_clearError(Mt29f *chip)
419 static void initPio(void)
422 * TODO: put following stuff in hw_ file dependent (and configurable cs?)
423 * Parameters for MT29F8G08AAD
425 pmc_periphEnable(PIOA_ID);
426 pmc_periphEnable(PIOC_ID);
427 pmc_periphEnable(PIOD_ID);
429 PIO_PERIPH_SEL(PIOA_BASE, MT29F_PINS_PORTA, MT29F_PERIPH_PORTA);
430 PIOA_PDR = MT29F_PINS_PORTA;
431 PIOA_PUER = MT29F_PINS_PORTA;
433 PIO_PERIPH_SEL(PIOC_BASE, MT29F_PINS_PORTC, MT29F_PERIPH_PORTC);
434 PIOC_PDR = MT29F_PINS_PORTC;
435 PIOC_PUER = MT29F_PINS_PORTC;
437 PIO_PERIPH_SEL(PIOD_BASE, MT29F_PINS_PORTD, MT29F_PERIPH_PORTD);
438 PIOD_PDR = MT29F_PINS_PORTD;
439 PIOD_PUER = MT29F_PINS_PORTD;
441 pmc_periphEnable(SMC_SDRAMC_ID);
445 static void initSmc(void)
447 SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0)
448 | SMC_SETUP_NCS_WR_SETUP(0)
449 | SMC_SETUP_NRD_SETUP(0)
450 | SMC_SETUP_NCS_RD_SETUP(0);
452 SMC_PULSE0 = SMC_PULSE_NWE_PULSE(2)
453 | SMC_PULSE_NCS_WR_PULSE(3)
454 | SMC_PULSE_NRD_PULSE(2)
455 | SMC_PULSE_NCS_RD_PULSE(3);
457 SMC_CYCLE0 = SMC_CYCLE_NWE_CYCLE(3)
458 | SMC_CYCLE_NRD_CYCLE(3);
460 SMC_TIMINGS0 = SMC_TIMINGS_TCLR(1)
461 | SMC_TIMINGS_TADL(6)
465 | SMC_TIMINGS_RBNSEL(7)
468 SMC_MODE0 = SMC_MODE_READ_MODE
469 | SMC_MODE_WRITE_MODE;
471 SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64
473 | SMC_CFG_DTOMUL_X1048576
474 | SMC_CFG_DTOCYC(0xF)
478 // Disable SMC interrupts, reset and enable NFC controller
481 SMC_CTRL = SMC_CTRL_NFCEN;
483 // Enable ECC, 1 ECC per 256 bytes
484 SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST;
485 SMC_ECC_MD = SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 | SMC_ECC_MD_TYPCORREC_C256B;
489 void mt29f_init(Mt29f *chip)
494 mt29f_clearError(chip);