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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief Micron MT29F serial NAND driver for SAM3's static memory controller.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "mt29f_sam3.h"
39 #include "cfg/cfg_mt29f.h"
41 // Define log settings for cfg/log.h
42 #define LOG_LEVEL CONFIG_MT29F_LOG_LEVEL
43 #define LOG_FORMAT CONFIG_MT29F_LOG_FORMAT
46 #include <cfg/macros.h>
49 #include <io/kblock.h>
51 #include <drv/timer.h>
52 #include <drv/mt29f.h>
54 #include <cpu/power.h> /* cpu_relax() */
55 #include <cpu/types.h>
57 #include <string.h> /* memcpy() */
59 // Timeout for NAND operations in ms
60 #define MT29F_TMOUT 100
62 // NAND flash status codes
63 #define MT29F_STATUS_READY BV(6)
64 #define MT29F_STATUS_ERROR BV(0)
66 // NAND flash commands
67 #define MT29F_CMD_READ_1 0x00
68 #define MT29F_CMD_READ_2 0x30
69 #define MT29F_CMD_COPYBACK_READ_1 0x00
70 #define MT29F_CMD_COPYBACK_READ_2 0x35
71 #define MT29F_CMD_COPYBACK_PROGRAM_1 0x85
72 #define MT29F_CMD_COPYBACK_PROGRAM_2 0x10
73 #define MT29F_CMD_RANDOM_OUT 0x05
74 #define MT29F_CMD_RANDOM_OUT_2 0xE0
75 #define MT29F_CMD_RANDOM_IN 0x85
76 #define MT29F_CMD_READID 0x90
77 #define MT29F_CMD_WRITE_1 0x80
78 #define MT29F_CMD_WRITE_2 0x10
79 #define MT29F_CMD_ERASE_1 0x60
80 #define MT29F_CMD_ERASE_2 0xD0
81 #define MT29F_CMD_STATUS 0x70
82 #define MT29F_CMD_RESET 0xFF
84 // Addresses for sending command, addresses and data bytes to flash
85 #define MT29F_CMD_ADDR 0x60400000
86 #define MT29F_ADDR_ADDR 0x60200000
87 #define MT29F_DATA_ADDR 0x60000000
97 * Translate flash page index plus a byte offset
98 * in the five address cycles format needed by NAND.
100 * Cycles in x8 mode as the MT29F2G08AAD
101 * CA = column addr, PA = page addr, BA = block addr
103 * Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
104 * -------------------------------------------------------
105 * First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
106 * Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
107 * Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
108 * Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
109 * Fifth LOW LOW LOW LOW LOW LOW LOW BA16
111 static void mt29f_getAddrCycles(block_idx_t page, size_t offset, uint32_t *cycle0, uint32_t *cycle1234)
113 uint32_t addr = (page * MT29F_PAGE_SIZE) + offset;
116 * offset nibbles 77776666 55554444 33332222 11110000
117 * cycle1234 -------7 66665555 ----4444 33332222
120 *cycle0 = addr & 0xff;
121 *cycle1234 = ((addr >> 8) & 0x00000fff) | ((addr >> 4) & 0x01ff0000);
123 LOG_INFO("mt29f addr: %lx %lx\n", *cycle1234, *cycle0);
127 INLINE bool mt29f_isBusy(void)
129 return HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000;
132 INLINE bool mt29f_isCmdDone(void)
134 return SMC_SR & SMC_SR_CMDDONE;
137 static bool mt29f_waitReadyBusy(void)
139 time_t start = timer_clock();
141 while (!(SMC_SR & SMC_SR_RB_EDGE0))
144 if (timer_clock() - start > MT29F_TMOUT)
146 LOG_INFO("mt29f: R/B timeout\n");
155 * Wait for transfer to complete until timeout.
156 * If transfer completes return true, false in case of timeout.
158 static bool mt29f_waitTransferComplete(void)
160 time_t start = timer_clock();
162 while (!(SMC_SR & SMC_SR_XFRDONE))
165 if (timer_clock() - start > MT29F_TMOUT)
167 LOG_INFO("mt29f: xfer complete timeout\n");
177 * Send command to NAND and wait for completion.
179 static void mt29f_sendCommand(uint32_t cmd,
180 int num_cycles, uint32_t cycle0, uint32_t cycle1234)
184 while (mt29f_isBusy());
189 cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd);
190 *cmd_addr = cycle1234;
192 while (!mt29f_isCmdDone());
196 static bool mt29f_isOperationComplete(void)
201 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
202 MT29F_CMD_STATUS << 2,
205 status = (uint8_t)HWREG(MT29F_DATA_ADDR);
206 return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR);
210 static void mt29f_reset(void)
213 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
214 MT29F_CMD_RESET << 2,
217 mt29f_waitReadyBusy();
222 * Erase the whole block containing given page.
224 int mt29f_blockErase(Mt29f *fls, block_idx_t page)
229 mt29f_getAddrCycles(page, 0, &cycle0, &cycle1234);
232 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 |
233 (MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2),
234 3, 0, cycle1234 >> 8);
236 mt29f_waitReadyBusy();
238 if (!mt29f_isOperationComplete())
240 LOG_ERR("mt29f: error erasing block\n");
241 fls->hw->status |= MT29F_ERR_ERASE;
250 * Read Device ID and configuration codes.
252 bool mt29f_getDevId(Mt29f *fls, uint8_t dev_id[5])
254 memset(dev_id, 0x66, 5);
255 memset((void *)NFC_SRAM_BASE_ADDR, 0x77, 2048);
258 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_ONE |
259 MT29F_CMD_READID << 2,
262 mt29f_waitReadyBusy();
263 if (!mt29f_waitTransferComplete())
265 LOG_ERR("mt29f: getDevId timeout\n");
266 fls->hw->status |= MT29F_ERR_RD_TMOUT;
270 memcpy(dev_id, (void *)NFC_SRAM_BASE_ADDR, 5);
275 static size_t mt29f_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size)
277 Mt29f *fls = FLASH_CAST(blk);
282 ASSERT(size == blk->blk_size);
284 LOG_INFO("mt29f_readDirect\n");
286 mt29f_getAddrCycles(idx, 0, &cycle0, &cycle1234);
289 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE | NFC_CMD_VCMD2 |
290 (MT29F_CMD_READ_2 << 10) | (MT29F_CMD_READ_1 << 2),
291 5, cycle0, cycle1234);
293 mt29f_waitReadyBusy();
294 if (!mt29f_waitTransferComplete())
296 LOG_ERR("mt29f: read timeout\n");
297 fls->hw->status |= MT29F_ERR_RD_TMOUT;
301 if (!kblock_buffered(blk) && (buf != (void *)NFC_SRAM_BASE_ADDR))
302 memcpy(buf, (void *)NFC_SRAM_BASE_ADDR, size);
308 static size_t mt29f_writeDirect(struct KBlock *blk, block_idx_t idx, const void *_buf, size_t offset, size_t size)
310 Mt29f *fls = FLASH_CAST(blk);
315 ASSERT(size == blk->blk_size);
317 LOG_INFO("mt29f_writeDirect\n");
319 if (!kblock_buffered(blk) && (_buf != (void *)NFC_SRAM_BASE_ADDR))
320 memcpy((void *)NFC_SRAM_BASE_ADDR, _buf, size);
322 mt29f_getAddrCycles(idx, 0, &cycle0, &cycle1234);
325 NFC_CMD_NFCCMD | NFC_CMD_NFCWR | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE |
326 MT29F_CMD_WRITE_1 << 2,
327 5, cycle0, cycle1234);
329 if (!mt29f_waitTransferComplete())
331 LOG_ERR("mt29f: write timeout\n");
332 fls->hw->status |= MT29F_ERR_WR_TMOUT;
337 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
338 MT29F_CMD_WRITE_2 << 2,
341 mt29f_waitReadyBusy();
343 if (!mt29f_isOperationComplete())
345 LOG_ERR("mt29f: error writing page\n");
346 fls->hw->status |= MT29F_ERR_WRITE;
354 static int mt29f_error(struct KBlock *blk)
356 Mt29f *fls = FLASH_CAST(blk);
357 return fls->hw->status;
361 static void mt29f_clearerror(struct KBlock *blk)
363 Mt29f *fls = FLASH_CAST(blk);
368 static const KBlockVTable mt29f_buffered_vt =
370 .readDirect = mt29f_readDirect,
371 .writeDirect = mt29f_writeDirect,
373 .readBuf = kblock_swReadBuf,
374 .writeBuf = kblock_swWriteBuf,
375 .load = kblock_swLoad,
376 .store = kblock_swStore,
378 .close = kblock_swClose,
380 .error = mt29f_error,
381 .clearerr = mt29f_clearerror,
385 static const KBlockVTable mt29f_unbuffered_vt =
387 .readDirect = mt29f_readDirect,
388 .writeDirect = mt29f_writeDirect,
390 .close = kblock_swClose,
392 .error = mt29f_error,
393 .clearerr = mt29f_clearerror,
397 static struct Mt29fHardware mt29f_hw;
400 static void common_init(Mt29f *fls)
402 memset(fls, 0, sizeof(*fls));
403 DB(fls->blk.priv.type = KBT_MT29F);
407 fls->blk.blk_size = MT29F_PAGE_SIZE;
408 fls->blk.blk_cnt = MT29F_SIZE / MT29F_PAGE_SIZE;
411 * TODO: put following stuff in hw_ file dependent (and configurable cs?)
412 * Parameters for MT29F8G08AAD
414 pmc_periphEnable(PIOA_ID);
415 pmc_periphEnable(PIOC_ID);
416 pmc_periphEnable(PIOD_ID);
418 PIO_PERIPH_SEL(PIOA_BASE, MT29F_PINS_PORTA, MT29F_PERIPH_PORTA);
419 PIOA_PDR = MT29F_PINS_PORTA;
420 PIOA_PUER = MT29F_PINS_PORTA;
422 PIO_PERIPH_SEL(PIOC_BASE, MT29F_PINS_PORTC, MT29F_PERIPH_PORTC);
423 PIOC_PDR = MT29F_PINS_PORTC;
424 PIOC_PUER = MT29F_PINS_PORTC;
426 PIO_PERIPH_SEL(PIOD_BASE, MT29F_PINS_PORTD, MT29F_PERIPH_PORTD);
427 PIOD_PDR = MT29F_PINS_PORTD;
428 PIOD_PUER = MT29F_PINS_PORTD;
430 pmc_periphEnable(SMC_SDRAMC_ID);
432 SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0)
433 | SMC_SETUP_NCS_WR_SETUP(0)
434 | SMC_SETUP_NRD_SETUP(0)
435 | SMC_SETUP_NCS_RD_SETUP(0);
437 SMC_PULSE0 = SMC_PULSE_NWE_PULSE(2)
438 | SMC_PULSE_NCS_WR_PULSE(3)
439 | SMC_PULSE_NRD_PULSE(2)
440 | SMC_PULSE_NCS_RD_PULSE(3);
442 SMC_CYCLE0 = SMC_CYCLE_NWE_CYCLE(3)
443 | SMC_CYCLE_NRD_CYCLE(3);
445 SMC_TIMINGS0 = SMC_TIMINGS_TCLR(1)
446 | SMC_TIMINGS_TADL(6)
450 | SMC_TIMINGS_RBNSEL(7)
453 SMC_MODE0 = SMC_MODE_READ_MODE
454 | SMC_MODE_WRITE_MODE;
456 SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64
458 | SMC_CFG_DTOMUL_X1048576
459 | SMC_CFG_DTOCYC(0xF);
461 // Disable SMC interrupts, reset and enable NFC controller
464 SMC_CTRL = SMC_CTRL_NFCEN;
470 void mt29f_init(Mt29f *fls)
473 fls->blk.priv.vt = &mt29f_buffered_vt;
474 fls->blk.priv.flags |= KB_BUFFERED;
475 fls->blk.priv.buf = (void *)NFC_SRAM_BASE_ADDR;
477 // Load the first block in the cache
478 mt29f_readDirect(&fls->blk, 0, (void *)NFC_SRAM_BASE_ADDR, 0, MT29F_PAGE_SIZE);
482 void mt29f_initUnbuffered(Mt29f *fls)
485 fls->blk.priv.vt = &mt29f_unbuffered_vt;