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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief Micron MT29F serial NAND driver for SAM3's static memory controller.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "mt29f_sam3.h"
39 #include "cfg/cfg_mt29f.h"
41 // Define log settings for cfg/log.h
42 #define LOG_LEVEL CONFIG_MT29F_LOG_LEVEL
43 #define LOG_FORMAT CONFIG_MT29F_LOG_FORMAT
46 #include <cfg/macros.h>
50 #include <drv/timer.h>
51 #include <drv/mt29f.h>
53 #include <cpu/power.h> /* cpu_relax() */
54 #include <cpu/types.h>
56 #include <string.h> /* memcpy() */
58 // Timeout for NAND operations in ms
59 #define MT29F_TMOUT 100
61 // NAND flash status codes
62 #define MT29F_STATUS_READY BV(6)
63 #define MT29F_STATUS_ERROR BV(0)
65 // NAND flash commands
66 #define MT29F_CMD_READ_1 0x00
67 #define MT29F_CMD_READ_2 0x30
68 #define MT29F_CMD_COPYBACK_READ_1 0x00
69 #define MT29F_CMD_COPYBACK_READ_2 0x35
70 #define MT29F_CMD_COPYBACK_PROGRAM_1 0x85
71 #define MT29F_CMD_COPYBACK_PROGRAM_2 0x10
72 #define MT29F_CMD_RANDOM_OUT 0x05
73 #define MT29F_CMD_RANDOM_OUT_2 0xE0
74 #define MT29F_CMD_RANDOM_IN 0x85
75 #define MT29F_CMD_READID 0x90
76 #define MT29F_CMD_WRITE_1 0x80
77 #define MT29F_CMD_WRITE_2 0x10
78 #define MT29F_CMD_ERASE_1 0x60
79 #define MT29F_CMD_ERASE_2 0xD0
80 #define MT29F_CMD_STATUS 0x70
81 #define MT29F_CMD_RESET 0xFF
83 // Addresses for sending command, addresses and data bytes to flash
84 #define MT29F_CMD_ADDR 0x60400000
85 #define MT29F_ADDR_ADDR 0x60200000
86 #define MT29F_DATA_ADDR 0x60000000
88 // Get chip select mask for command register
89 #define MT29F_CSID(chip) (((chip)->chip_select << NFC_CMD_CSID_SHIFT) & NFC_CMD_CSID_MASK)
93 * Translate flash page index plus a byte offset
94 * in the five address cycles format needed by NAND.
96 * Cycles in x8 mode as the MT29F2G08AAD
97 * CA = column addr, PA = page addr, BA = block addr
99 * Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
100 * -------------------------------------------------------
101 * First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
102 * Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
103 * Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
104 * Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
105 * Fifth LOW LOW LOW LOW LOW LOW LOW BA16
107 static void getAddrCycles(uint32_t page, uint16_t offset, uint32_t *cycle0, uint32_t *cycle1234)
109 ASSERT(offset < MT29F_PAGE_SIZE);
111 *cycle0 = offset & 0xff;
112 *cycle1234 = (page << 8) | ((offset >> 8) & 0xf);
114 LOG_INFO("mt29f addr: %lx %lx\n", *cycle1234, *cycle0);
118 INLINE bool nfcIsBusy(void)
120 return HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000;
123 INLINE bool isCmdDone(void)
125 return SMC_SR & SMC_SR_CMDDONE;
128 static bool waitReadyBusy(void)
130 time_t start = timer_clock();
132 while (!(SMC_SR & SMC_SR_RB_EDGE0))
135 if (timer_clock() - start > MT29F_TMOUT)
137 LOG_INFO("mt29f: R/B timeout\n");
146 * Wait for transfer to complete until timeout.
147 * If transfer completes return true, false in case of timeout.
149 static bool waitTransferComplete(void)
151 time_t start = timer_clock();
153 while (!(SMC_SR & SMC_SR_XFRDONE))
156 if (timer_clock() - start > MT29F_TMOUT)
158 LOG_INFO("mt29f: xfer complete timeout\n");
168 * Send command to NAND and wait for completion.
170 static void sendCommand(uint32_t cmd,
171 int num_cycles, uint32_t cycle0, uint32_t cycle1234)
180 cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd);
181 *cmd_addr = cycle1234;
183 while (!isCmdDone());
187 static bool isOperationComplete(Mt29f *chip)
191 sendCommand(MT29F_CSID(chip) |
192 NFC_CMD_NFCCMD | NFC_CMD_ACYCLE_NONE |
193 MT29F_CMD_STATUS << 2,
196 status = (uint8_t)HWREG(MT29F_DATA_ADDR);
197 return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR);
201 static void chipReset(Mt29f *chip)
203 sendCommand(MT29F_CSID(chip) |
204 NFC_CMD_NFCCMD | NFC_CMD_ACYCLE_NONE |
205 MT29F_CMD_RESET << 2,
213 * Erase the whole block containing given page.
215 int mt29f_blockErase(Mt29f *chip, uint32_t page)
220 getAddrCycles(page, 0, &cycle0, &cycle1234);
222 sendCommand(MT29F_CSID(chip) |
223 NFC_CMD_NFCCMD | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 |
224 (MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2),
225 3, 0, cycle1234 >> 8);
229 if (!isOperationComplete(chip))
231 LOG_ERR("mt29f: error erasing block\n");
232 chip->status |= MT29F_ERR_ERASE;
241 * Read Device ID and configuration codes.
243 bool mt29f_getDevId(Mt29f *chip, uint8_t dev_id[5])
245 sendCommand(MT29F_CSID(chip) |
246 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | NFC_CMD_ACYCLE_ONE |
247 MT29F_CMD_READID << 2,
251 if (!waitTransferComplete())
253 LOG_ERR("mt29f: getDevId timeout\n");
254 chip->status |= MT29F_ERR_RD_TMOUT;
258 memcpy(dev_id, (void *)NFC_SRAM_BASE_ADDR, 5);
263 static bool checkEcc(void)
265 uint32_t sr1 = SMC_ECC_SR1;
269 LOG_INFO("ECC error, ECC_SR1=0x%lx\n", sr1);
277 static bool mt29f_readPage(Mt29f *chip, uint32_t page, uint16_t offset)
282 LOG_INFO("mt29f_readPage: page 0x%lx off 0x%x\n", page, offset);
284 getAddrCycles(page, offset, &cycle0, &cycle1234);
286 sendCommand(MT29F_CSID(chip) |
287 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | NFC_CMD_ACYCLE_FIVE | NFC_CMD_VCMD2 |
288 (MT29F_CMD_READ_2 << 10) | (MT29F_CMD_READ_1 << 2),
289 5, cycle0, cycle1234);
292 if (!waitTransferComplete())
294 LOG_ERR("mt29f: read timeout\n");
295 chip->status |= MT29F_ERR_RD_TMOUT;
304 * Read page data and ECC, checking for errors.
305 * TODO: fix errors with ECC when possible.
307 bool mt29f_read(Mt29f *chip, uint32_t page, void *buf, uint16_t size)
309 ASSERT(size <= MT29F_DATA_SIZE);
311 if (!mt29f_readPage(chip, page, 0))
314 memcpy(buf, (void *)NFC_SRAM_BASE_ADDR, size);
321 * Write data in NFC SRAM buffer to a NAND page, starting at a given offset.
322 * Usually offset will be 0 to write data or MT29F_DATA_SIZE to write the spare
325 * According to datasheet to get ECC computed by hardware is sufficient
326 * to write the main area. But it seems that in that way the last ECC_PR
327 * register is not generated. The workaround is to write data and dummy (ff)
328 * spare data in one write, at this point the last ECC_PR is correct and
329 * ECC data can be written in the spare area with a second program operation.
331 static bool mt29f_writePage(Mt29f *chip, uint32_t page, uint16_t offset)
336 LOG_INFO("mt29f_writePage: page 0x%lx off 0x%x\n", page, offset);
338 getAddrCycles(page, offset, &cycle0, &cycle1234);
340 sendCommand(MT29F_CSID(chip) |
341 NFC_CMD_NFCCMD | NFC_CMD_NFCWR | NFC_CMD_NFCEN | NFC_CMD_ACYCLE_FIVE |
342 MT29F_CMD_WRITE_1 << 2,
343 5, cycle0, cycle1234);
345 if (!waitTransferComplete())
347 LOG_ERR("mt29f: write timeout\n");
348 chip->status |= MT29F_ERR_WR_TMOUT;
352 sendCommand(MT29F_CSID(chip) |
353 NFC_CMD_NFCCMD | NFC_CMD_ACYCLE_NONE |
354 MT29F_CMD_WRITE_2 << 2,
359 if (!isOperationComplete(chip))
361 LOG_ERR("mt29f: error writing page\n");
362 chip->status |= MT29F_ERR_WRITE;
371 * Write data in a page.
373 static bool mt29f_writePageData(Mt29f *chip, uint32_t page, const void *buf, uint16_t size)
375 ASSERT(size <= MT29F_DATA_SIZE);
377 memset((void *)NFC_SRAM_BASE_ADDR, 0xff, MT29F_PAGE_SIZE);
378 memcpy((void *)NFC_SRAM_BASE_ADDR, buf, size);
380 return mt29f_writePage(chip, page, 0);
385 * Write the ECC for a page.
387 * ECC data are extracted from ECC_PRx registers and written
388 * in the page's spare area.
389 * For 2048 bytes pages and 1 ECC word each 256 bytes,
390 * 24 bytes of ECC data are stored.
392 static bool mt29f_writePageEcc(Mt29f *chip, uint32_t page)
395 uint32_t *buf = (uint32_t *)NFC_SRAM_BASE_ADDR;
397 memset((void *)NFC_SRAM_BASE_ADDR, 0xff, MT29F_SPARE_SIZE);
399 for (i = 0; i < MT29F_ECC_NWORDS; i++)
400 buf[i] = *((reg32_t *)(SMC_BASE + SMC_ECC_PR0_OFF) + i);
402 return mt29f_writePage(chip, page, MT29F_DATA_SIZE);
406 bool mt29f_write(Mt29f *chip, uint32_t page, const void *buf, uint16_t size)
409 mt29f_writePageData(chip, page, buf, size) &&
410 mt29f_writePageEcc(chip, page);
414 int mt29f_error(Mt29f *chip)
420 void mt29f_clearError(Mt29f *chip)
426 static void initPio(void)
429 * TODO: put following stuff in hw_ file dependent
430 * Parameters for MT29F8G08AAD
432 pmc_periphEnable(PIOA_ID);
433 pmc_periphEnable(PIOC_ID);
434 pmc_periphEnable(PIOD_ID);
436 PIO_PERIPH_SEL(PIOA_BASE, MT29F_PINS_PORTA, MT29F_PERIPH_PORTA);
437 PIOA_PDR = MT29F_PINS_PORTA;
438 PIOA_PUER = MT29F_PINS_PORTA;
440 PIO_PERIPH_SEL(PIOC_BASE, MT29F_PINS_PORTC, MT29F_PERIPH_PORTC);
441 PIOC_PDR = MT29F_PINS_PORTC;
442 PIOC_PUER = MT29F_PINS_PORTC;
444 PIO_PERIPH_SEL(PIOD_BASE, MT29F_PINS_PORTD, MT29F_PERIPH_PORTD);
445 PIOD_PDR = MT29F_PINS_PORTD;
446 PIOD_PUER = MT29F_PINS_PORTD;
448 pmc_periphEnable(SMC_SDRAMC_ID);
452 static void initSmc(void)
454 SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0)
455 | SMC_SETUP_NCS_WR_SETUP(0)
456 | SMC_SETUP_NRD_SETUP(0)
457 | SMC_SETUP_NCS_RD_SETUP(0);
459 SMC_PULSE0 = SMC_PULSE_NWE_PULSE(2)
460 | SMC_PULSE_NCS_WR_PULSE(3)
461 | SMC_PULSE_NRD_PULSE(2)
462 | SMC_PULSE_NCS_RD_PULSE(3);
464 SMC_CYCLE0 = SMC_CYCLE_NWE_CYCLE(3)
465 | SMC_CYCLE_NRD_CYCLE(3);
467 SMC_TIMINGS0 = SMC_TIMINGS_TCLR(1)
468 | SMC_TIMINGS_TADL(6)
472 | SMC_TIMINGS_RBNSEL(7)
475 SMC_MODE0 = SMC_MODE_READ_MODE
476 | SMC_MODE_WRITE_MODE;
478 SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64
480 | SMC_CFG_DTOMUL_X1048576
481 | SMC_CFG_DTOCYC(0xF)
485 // Disable SMC interrupts, reset and enable NFC controller
488 SMC_CTRL = SMC_CTRL_NFCEN;
490 // Enable ECC, 1 ECC per 256 bytes
491 SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST;
492 SMC_ECC_MD = SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 | SMC_ECC_MD_TYPCORREC_C256B;
496 void mt29f_init(Mt29f *chip, uint8_t chip_select)
498 memset(chip, 0, sizeof(Mt29f));
500 chip->chip_select = chip_select;