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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief Micron MT29F serial NAND driver for SAM3's static memory controller.
35 * \author Stefano Fedrigo <aleph@develer.com>
38 #include "mt29f_sam3.h"
39 #include "cfg/cfg_mt29f.h"
41 // Define log settings for cfg/log.h
42 #define LOG_LEVEL CONFIG_MT29F_LOG_LEVEL
43 #define LOG_FORMAT CONFIG_MT29F_LOG_FORMAT
46 #include <cfg/macros.h>
49 #include <io/kblock.h>
51 #include <drv/timer.h>
52 #include <drv/mt29f.h>
54 #include <cpu/power.h> /* cpu_relax() */
55 #include <cpu/types.h>
57 #include <string.h> /* memcpy() */
60 // NAND flash status codes
61 #define MT29F_STATUS_READY BV(6)
62 #define MT29F_STATUS_ERROR BV(0)
64 // NAND flash commands
65 #define MT29F_CMD_READ_1 0x00
66 #define MT29F_CMD_READ_2 0x30
67 #define MT29F_CMD_COPYBACK_READ_1 0x00
68 #define MT29F_CMD_COPYBACK_READ_2 0x35
69 #define MT29F_CMD_COPYBACK_PROGRAM_1 0x85
70 #define MT29F_CMD_COPYBACK_PROGRAM_2 0x10
71 #define MT29F_CMD_RANDOM_OUT 0x05
72 #define MT29F_CMD_RANDOM_OUT_2 0xE0
73 #define MT29F_CMD_RANDOM_IN 0x85
74 #define MT29F_CMD_READID 0x90
75 #define MT29F_CMD_WRITE_1 0x80
76 #define MT29F_CMD_WRITE_2 0x10
77 #define MT29F_CMD_ERASE_1 0x60
78 #define MT29F_CMD_ERASE_2 0xD0
79 #define MT29F_CMD_STATUS 0x70
80 #define MT29F_CMD_RESET 0xFF
90 * Translate flash page index plus a byte offset
91 * in the five address cycles format needed by NAND.
93 * Cycles in x8 mode as the MT29F2G08AAD
94 * CA = column addr, PA = page addr, BA = block addr
96 * Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
97 * -------------------------------------------------------
98 * First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
99 * Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
100 * Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
101 * Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
102 * Fifth LOW LOW LOW LOW LOW LOW LOW BA16
104 static void mt29f_getAddrCycles(block_idx_t page, size_t offset, uint32_t *cycle0, uint32_t *cycle1234)
106 uint32_t addr = (page * MT29F_PAGE_SIZE) + offset;
109 * offset nibbles 77776666 55554444 33332222 11110000
110 * cycle1234 -------7 66665555 ----4444 33332222
113 *cycle0 = addr & 0xff;
114 *cycle1234 = ((addr >> 8) & 0x00000fff) | ((addr >> 4) & 0x01ff0000);
118 INLINE bool mt29f_isBusy(void)
120 return HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000;
123 INLINE bool mt29f_isCmdDone(void)
125 return SMC_SR & SMC_SR_CMDDONE;
128 INLINE bool mt29f_isReadyBusy(void)
130 return SMC_SR & SMC_SR_RB_EDGE0;
133 INLINE bool mt29f_isTransferComplete(void)
135 return SMC_SR & SMC_SR_XFRDONE;
140 * Send command to NAND and wait for completion.
142 static void mt29f_sendCommand(uint32_t cmd, uint32_t cycle0, uint32_t cycle1234)
146 while (mt29f_isBusy());
150 cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd);
151 *cmd_addr = cycle1234;
153 while (!mt29f_isCmdDone());
157 static bool mt29f_isOperationComplete(void)
162 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
163 MT29F_CMD_STATUS << 2, 0, 0);
165 status = (uint8_t)HWREG(MT29F_DATA_ADDR);
166 return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR);
172 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
173 MT29F_CMD_RESET << 2,
174 0, /* Dummy address cylce 1,2,3,4.*/
175 0 /* Dummy address cylce 0.*/
179 * Erase block at given offset.
181 int mt29f_blockErase(Mt29f *fls, block_idx_t page)
186 mt29f_getAddrCycles(page, 0, &cycle0, &cycle1234);
189 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 |
190 (MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2),
193 while (!mt29f_isReadyBusy());
195 if (!mt29f_isOperationComplete())
197 LOG_ERR("mt29f: error erasing block\n");
198 fls->hw->status |= MT29F_ERR_ERASE;
206 static size_t mt29f_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size)
212 ASSERT(size == blk->blk_size);
214 mt29f_getAddrCycles(idx, 0, &cycle0, &cycle1234);
217 NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE | NFC_CMD_VCMD2 |
218 (MT29F_CMD_READ_2 << 10) | (MT29F_CMD_READ_1 << 2),
221 while (!mt29f_isReadyBusy());
222 while (!mt29f_isTransferComplete());
224 if (!kblock_buffered(blk))
226 // Make sure user is not buffering just in NFC controller SRAM
227 ASSERT((buf < (void *)NFC_CMD_BASE_ADDR) || (buf > (void *)(NFC_CMD_BASE_ADDR + MT29F_PAGE_SIZE)));
228 memcpy(buf, (void *)NFC_CMD_BASE_ADDR, size);
235 static size_t mt29f_writeDirect(struct KBlock *blk, block_idx_t idx, const void *_buf, size_t offset, size_t size)
237 Mt29f *fls = FLASH_CAST(blk);
242 ASSERT(size == blk->blk_size);
244 if (!kblock_buffered(blk))
246 // Make sure user is not buffering just in NFC controller SRAM
247 ASSERT((_buf < (void *)NFC_CMD_BASE_ADDR) || (_buf > (void *)(NFC_CMD_BASE_ADDR + MT29F_PAGE_SIZE)));
248 memcpy((void *)NFC_CMD_BASE_ADDR, _buf, size);
251 mt29f_getAddrCycles(idx, 0, &cycle0, &cycle1234);
254 NFC_CMD_NFCCMD | NFC_CMD_NFCWR | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE |
255 MT29F_CMD_WRITE_1 << 2,
258 while (!mt29f_isTransferComplete());
261 NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
262 MT29F_CMD_WRITE_2 << 2,
265 while (!mt29f_isReadyBusy());
267 if (!mt29f_isOperationComplete())
269 LOG_ERR("mt29f: error writing page\n");
270 fls->hw->status |= MT29F_ERR_WRITE;
278 static int mt29f_error(struct KBlock *blk)
280 Mt29f *fls = FLASH_CAST(blk);
281 return fls->hw->status;
285 static void mt29f_clearerror(struct KBlock *blk)
287 Mt29f *fls = FLASH_CAST(blk);
292 static const KBlockVTable mt29f_buffered_vt =
294 .readDirect = mt29f_readDirect,
295 .writeDirect = mt29f_writeDirect,
297 .readBuf = kblock_swReadBuf,
298 .writeBuf = kblock_swWriteBuf,
299 .load = kblock_swLoad,
300 .store = kblock_swStore,
302 .close = kblock_swClose,
304 .error = mt29f_error,
305 .clearerr = mt29f_clearerror,
309 static const KBlockVTable mt29f_unbuffered_vt =
311 .readDirect = mt29f_readDirect,
312 .writeDirect = mt29f_writeDirect,
314 .close = kblock_swClose,
316 .error = mt29f_error,
317 .clearerr = mt29f_clearerror,
321 static struct Mt29fHardware mt29f_hw;
324 static void common_init(Mt29f *fls)
326 memset(fls, 0, sizeof(*fls));
327 DB(fls->blk.priv.type = KBT_MT29F);
331 fls->blk.blk_size = MT29F_PAGE_SIZE;
332 fls->blk.blk_cnt = MT29F_SIZE / MT29F_PAGE_SIZE;
335 * TODO: put following stuff in hw_ file dependent (and configurable cs?)
336 * Parameters for MT29F8G08AAD
338 pmc_periphEnable(PIOA_ID);
339 pmc_periphEnable(PIOC_ID);
340 pmc_periphEnable(PIOD_ID);
342 PIO_PERIPH_SEL(PIOA_BASE, MT29F_PINS_PORTA, MT29F_PERIPH_PORTA);
343 PIOA_PDR = MT29F_PINS_PORTA;
344 PIOA_PUER = MT29F_PINS_PORTA;
346 PIO_PERIPH_SEL(PIOC_BASE, MT29F_PINS_PORTC, MT29F_PERIPH_PORTC);
347 PIOC_PDR = MT29F_PINS_PORTC;
348 PIOC_PUER = MT29F_PINS_PORTC;
350 PIO_PERIPH_SEL(PIOD_BASE, MT29F_PINS_PORTD, MT29F_PERIPH_PORTD);
351 PIOD_PDR = MT29F_PINS_PORTD;
352 PIOD_PUER = MT29F_PINS_PORTD;
354 pmc_periphEnable(SMC_SDRAMC_ID);
356 SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0)
357 | SMC_SETUP_NCS_WR_SETUP(0)
358 | SMC_SETUP_NRD_SETUP(0)
359 | SMC_SETUP_NCS_RD_SETUP(0);
361 SMC_PULSE0 = SMC_PULSE_NWE_PULSE(2)
362 | SMC_PULSE_NCS_WR_PULSE(3)
363 | SMC_PULSE_NRD_PULSE(2)
364 | SMC_PULSE_NCS_RD_PULSE(3);
366 SMC_CYCLE0 = SMC_CYCLE_NWE_CYCLE(3)
367 | SMC_CYCLE_NRD_CYCLE(3);
369 SMC_TIMINGS0 = SMC_TIMINGS_TCLR(1)
370 | SMC_TIMINGS_TADL(6)
374 | SMC_TIMINGS_RBNSEL(7)
377 SMC_MODE0 = SMC_MODE_READ_MODE
378 | SMC_MODE_WRITE_MODE;
382 void mt29f_hw_init(Mt29f *fls)
385 fls->blk.priv.vt = &mt29f_buffered_vt;
386 fls->blk.priv.flags |= KB_BUFFERED;
387 fls->blk.priv.buf = (void *)NFC_CMD_BASE_ADDR;
389 // Load the first block in the cache
391 memcpy(fls->blk.priv.buf, start, fls->blk.blk_size);
395 void mt29f_hw_initUnbuffered(Mt29f *fls)
398 fls->blk.priv.vt = &mt29f_unbuffered_vt;