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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32 RTC driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include "clock_stm32.h"
40 #include <cfg/compiler.h>
41 #include <cfg/module.h>
42 #include <cfg/debug.h>
45 #include <io/stm32_pwr.h>
47 #include <cpu/power.h> // cpu_relax()
51 /* PWR registers base */
52 static struct PWR *PWR = (struct PWR *)PWR_BASE;
54 /* RTC clock source: LSE */
55 #define RTC_CLKSRC 0x00000100
56 /* RTC clock: 32768 Hz */
57 #define RTC_CLOCK 32768
58 /* RTC clock period (in ms) */
59 #define RTC_PERIOD 1000
61 /* RTC control register */
62 #define RTC_CRH (*(reg16_t *)(RTC_BASE + 0x00))
63 #define RTC_CRL (*(reg16_t *)(RTC_BASE + 0x04))
65 #define RTC_CRL_SECIE BV(0)
66 #define RTC_CRL_ALRIE BV(1)
67 #define RTC_CRL_OWIE BV(2)
69 #define RTC_CRL_SECF BV(0)
70 #define RTC_CRL_ALRF BV(1)
71 #define RTC_CRL_OWF BV(2)
72 #define RTC_CRL_RSF BV(3)
73 #define RTC_CRL_CNF BV(4)
74 #define RTC_CRL_RTOFF BV(5)
76 /* RTC prescaler load register */
77 #define RTC_PRLH (*(reg16_t *)(RTC_BASE + 0x08))
78 #define RTC_PRLL (*(reg16_t *)(RTC_BASE + 0x0c))
80 /* RTC prescaler divider register */
81 #define RTC_DIVH (*(reg16_t *)(RTC_BASE + 0x10))
82 #define RTC_DIVL (*(reg16_t *)(RTC_BASE + 0x14))
84 /* RTC counter register */
85 #define RTC_CNTH (*(reg16_t *)(RTC_BASE + 0x18))
86 #define RTC_CNTL (*(reg16_t *)(RTC_BASE + 0x1c))
88 /* RTC alarm register */
89 #define RTC_ALRH (*(reg16_t *)(RTC_BASE + 0x20))
90 #define RTC_ALRL (*(reg16_t *)(RTC_BASE + 0x24))
92 static void rtc_enterConfig(void)
94 /* Enter configuration mode */
95 RTC_CRL |= RTC_CRL_CNF;
98 static void rtc_exitConfig(void)
100 /* Exit from configuration mode */
101 RTC_CRL &= ~RTC_CRL_CNF;
102 while (!(RTC_CRL & RTC_CRL_RTOFF))
106 uint32_t rtc_time(void)
108 return (RTC_CNTH << 16) | RTC_CNTL;
111 void rtc_setTime(uint32_t val)
114 RTC_CNTH = (val >> 16) & 0xffff;
115 RTC_CNTL = val & 0xffff;
119 /* Initialize the RTC clock */
125 /* Enable clock for Power interface */
126 RCC->APB1ENR |= RCC_APB1_PWR;
128 /* Enable access to RTC registers */
129 PWR->CR |= PWR_CR_DBP;
132 RCC->BDCR |= RCC_BDCR_LSEON;
133 /* Wait for LSE ready */
134 while (!(RCC->BDCR & RCC_BDCR_LSERDY))
137 /* Set clock source and enable RTC peripheral */
138 RCC->BDCR |= RTC_CLKSRC | RCC_BDCR_RTCEN;
143 RTC_PRLH = ((RTC_PERIOD * RTC_CLOCK / 1000 - 1) >> 16) & 0xff;
144 RTC_PRLL = ((RTC_PERIOD * RTC_CLOCK / 1000 - 1)) & 0xffff;
148 /* Disable access to the RTC registers */
149 PWR->CR &= ~PWR_CR_DBP;