bertos/cpu/cortex-m3/drv/ser_lm3s.c

   1 /**
   2  * \file
   3  * <!--
   4  * This file is part of BeRTOS.
   5  *
   6  * Bertos is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  *
  20  * As a special exception, you may use this file as part of a free software
  21  * library without restriction.  Specifically, if other files instantiate
  22  * templates or use macros or inline functions from this file, or you compile
  23  * this file and link it with other files to produce an executable, this
  24  * file does not by itself cause the resulting executable to be covered by
  25  * the GNU General Public License.  This exception does not however
  26  * invalidate any other reasons why the executable file might be covered by
  27  * the GNU General Public License.
  28  *
  29  * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
  30  *
  31  * -->
  32  *
  33  * \brief LM3S1968 UART interface driver.
  34  *
  35  * \author Andrea Righi <arighi@develer.com>
  36  */
  37
  38 #include <cfg/macros.h> /* for BV() */
  39 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
  40 #include <drv/gpio_lm3s.h>
  41 #include <drv/ser_p.h>
  42 #include <drv/ser.h>
  43 #include <drv/irq_cm3.h>
  44 #include "cfg/cfg_ser.h"
  45 #include "ser_lm3s.h"
  46
  47 /* From the high-level serial driver */
  48 extern struct Serial *ser_handles[SER_CNT];
  49
  50 struct CM3Serial
  51 {
  52         struct SerialHardware hw;
  53         bool sending;
  54         uint32_t base;
  55         sysirq_t irq;
  56 };
  57
  58 /* Forward declaration */
  59 static struct CM3Serial UARTDesc[SER_CNT];
  60
  61 /* GPIO descriptor for UART pins */
  62 struct gpio_uart_info
  63 {
  64         /* GPIO base address register */
  65         uint32_t base;
  66         /* Pin(s) bitmask */
  67         uint8_t pins;
  68 };
  69
  70 /* Table to retrieve GPIO pins configuration to work as UART pins */
  71 static const struct gpio_uart_info gpio_uart[SER_CNT] =
  72 {
  73         /* UART0 */
  74         {
  75                 .base = GPIO_PORTA_BASE,
  76                 .pins = BV(1) | BV(0),
  77         },
  78         /* UART1 */
  79         {
  80                 .base = GPIO_PORTD_BASE,
  81                 .pins = BV(3) | BV(2),
  82         },
  83         /* UART2 */
  84         {
  85                 .base = GPIO_PORTG_BASE,
  86                 .pins = BV(1) | BV(0),
  87         },
  88 };
  89
  90 /* Clear the flags register */
  91 INLINE void lm3s_uartClear(uint32_t base)
  92 {
  93         HWREG(base + UART_O_FR) = 0;
  94 }
  95
  96 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud)
  97 {
  98         unsigned long div;
  99         bool hi_speed;
 100
 101         if (baud * 16 > CPU_FREQ)
 102         {
 103                 hi_speed = true;
 104                 baud /= 2;
 105         }
 106         div = (CPU_FREQ * 8 / baud + 1) / 2;
 107
 108         lm3s_uartDisable(base);
 109         if (hi_speed)
 110                 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
 111         else
 112                 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
 113         /* Set the baud rate */
 114         HWREG(base + UART_O_IBRD) = div / 64;
 115         HWREG(base + UART_O_FBRD) = div % 64;
 116         lm3s_uartClear(base);
 117         lm3s_uartEnable(base);
 118 }
 119
 120 void lm3s_uartSetParity(uint32_t base, int parity)
 121 {
 122         /* Set 8-bit word, one stop bit by default */
 123         uint32_t config = UART_LCRH_WLEN_8;
 124
 125         switch(parity)
 126         {
 127         case SER_PARITY_NONE:
 128                 break;
 129         case SER_PARITY_ODD:
 130                 config |= UART_LCRH_PEN;
 131                 break;
 132         case SER_PARITY_EVEN:
 133                 config |= UART_LCRH_EPS | UART_LCRH_PEN;
 134                 break;
 135         default:
 136                 ASSERT(0);
 137                 return;
 138         }
 139         lm3s_uartDisable(base);
 140         HWREG(base + UART_O_LCRH) = config;
 141         lm3s_uartClear(base);
 142         lm3s_uartEnable(base);
 143 }
 144
 145 void lm3s_uartInit(int port)
 146 {
 147         uint32_t reg_clock, base;
 148
 149         ASSERT(port >= 0 && port < SER_CNT);
 150
 151         base = UARTDesc[port].base;
 152         reg_clock = 1 << port;
 153
 154         /* Enable the peripheral clock */
 155         SYSCTL_RCGC1_R |= reg_clock;
 156         SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
 157         lm3s_busyWait(512);
 158
 159         /* Configure GPIO pins to work as UART pins */
 160         lm3s_gpioPinConfig(gpio_uart[port].base, gpio_uart[port].pins,
 161                         GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 162
 163         /* Set serial param: 115.200 bps, no parity */
 164         lm3s_uartSetBaudRate(base, 115200);
 165         lm3s_uartSetParity(base, SER_PARITY_NONE);
 166 }
 167
 168 static bool tx_sending(struct SerialHardware *_hw)
 169 {
 170         struct CM3Serial *hw = (struct CM3Serial *)_hw;
 171         return hw->sending;
 172 }
 173
 174 static void uart_irq_rx(int port)
 175 {
 176         struct FIFOBuffer *rxfifo = &ser_handles[port]->rxfifo;
 177         uint32_t base = UARTDesc[port].base;
 178         char c;
 179
 180         while (lm3s_uartRxReady(base))
 181         {
 182                 c = HWREG(base + UART_O_DR);
 183                 if (fifo_isfull(rxfifo))
 184                         ser_handles[port]->status |= SERRF_RXFIFOOVERRUN;
 185                 else
 186                         fifo_push(rxfifo, c);
 187         }
 188 }
 189
 190 static void uart_irq_tx(int port)
 191 {
 192         struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;
 193         uint32_t base = UARTDesc[port].base;
 194
 195         while (lm3s_uartTxReady(base))
 196         {
 197                 if (fifo_isempty(txfifo)) {
 198                         /*
 199                          * Disable TX empty interrupts if there're no more
 200                          * characters to transmit.
 201                          */
 202                         HWREG(base + UART_O_IM) &= ~UART_IM_TXIM;
 203                         UARTDesc[port].sending = false;
 204                         break;
 205                 }
 206                 HWREG(base + UART_O_DR) = fifo_pop(txfifo);
 207         }
 208 }
 209
 210 static void uart_common_irq_handler(int port)
 211 {
 212         uint32_t base = UARTDesc[port].base;
 213         uint32_t status;
 214
 215         /* Read and clear the IRQ status */
 216         status = HWREG(base + UART_O_RIS);
 217
 218         /* Process the IRQ */
 219         if (status & (UART_RIS_RXRIS | UART_RIS_RTRIS))
 220                 uart_irq_rx(port);
 221         if (status & UART_RIS_TXRIS)
 222                 uart_irq_tx(port);
 223 }
 224
 225 static void
 226 lm3s_uartIRQEnable(int port, sysirq_handler_t handler)
 227 {
 228         uint32_t base = UARTDesc[port].base;
 229         sysirq_t irq = UARTDesc[port].irq;
 230
 231         /* Register the IRQ handler */
 232         sysirq_setHandler(irq, handler);
 233         /* Enable RX interrupt in the UART interrupt mask register */
 234         HWREG(base + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM;
 235 }
 236
 237 static void lm3s_uartIRQDisable(int port)
 238 {
 239         uint32_t base = UARTDesc[port].base;
 240
 241         HWREG(base + UART_O_IM) &=
 242                         ~(UART_IM_TXIM | UART_IM_RXIM | UART_IM_RTIM);
 243 }
 244
 245 /* UART class definition */
 246 #define UART_PORT(port)                                                         \
 247         /* UART TX and RX buffers */                                            \
 248         static unsigned char                                                    \
 249                 uart ## port ## _txbuffer[CONFIG_UART ## port ## _TXBUFSIZE];   \
 250         static unsigned char                                                    \
 251                 uart ## port ## _rxbuffer[CONFIG_UART ## port ## _RXBUFSIZE];   \
 252                                                                                 \
 253         /* UART interrupt handler */                                            \
 254         static DECLARE_ISR(uart ## port ## _irq_handler)                        \
 255         {                                                                       \
 256                 uart_common_irq_handler(port);                                  \
 257         }                                                                       \
 258                                                                                 \
 259         /* UART public methods */                                               \
 260         static void                                                             \
 261         uart ## port ## _txStart(struct SerialHardware *_hw)                    \
 262         {                                                                       \
 263                 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;         \
 264                 struct CM3Serial *hw = (struct CM3Serial *)_hw;                 \
 265                                                                                 \
 266                 if (hw->sending)                                                \
 267                         return;                                                 \
 268                 lm3s_uartPutChar(UART ## port ## _BASE, fifo_pop(txfifo));      \
 269                 if (!fifo_isempty(txfifo))                                      \
 270                 {                                                               \
 271                         HWREG(UART ## port ## _BASE + UART_O_IM) |=             \
 272                                                  UART_IM_TXIM;                  \
 273                         hw->sending = true;                                     \
 274                 }                                                               \
 275         }                                                                       \
 276                                                                                 \
 277         static void                                                             \
 278         uart ## port ## _setbaudrate(UNUSED_ARG(struct SerialHardware *, hw),   \
 279                                                 unsigned long baud)             \
 280         {                                                                       \
 281                 lm3s_uartSetBaudRate(UART ## port ## _BASE, baud);              \
 282         }                                                                       \
 283                                                                                 \
 284         static void                                                             \
 285         uart ## port ## _setparity(UNUSED_ARG(struct SerialHardware *, hw),     \
 286                                                 int parity)                     \
 287         {                                                                       \
 288                 lm3s_uartSetParity(UART ## port ## _BASE, parity);              \
 289         }                                                                       \
 290                                                                                 \
 291         static void                                                             \
 292         uart ## port ## _cleanup(struct SerialHardware *_hw)                    \
 293         {                                                                       \
 294                 struct CM3Serial *hw = (struct CM3Serial *)_hw;                 \
 295                                                                                 \
 296                 hw->sending = false;                                            \
 297                 lm3s_uartIRQDisable(port);                                      \
 298                 lm3s_uartClear(UART ## port ## _BASE);                          \
 299                 lm3s_uartDisable(UART ## port ## _BASE);                        \
 300         }                                                                       \
 301                                                                                 \
 302         static void                                                             \
 303         uart ## port ## _init(UNUSED_ARG(struct SerialHardware *, hw),          \
 304                                 UNUSED_ARG(struct Serial *, ser))               \
 305         {                                                                       \
 306                 lm3s_uartInit(port);                                            \
 307                 lm3s_uartEnable(UART ## port ## _BASE);                         \
 308                 lm3s_uartIRQEnable(port, uart ## port ## _irq_handler);         \
 309         }                                                                       \
 310                                                                                 \
 311         /* UART operations */                                                   \
 312         static const struct SerialHardwareVT UART ## port ## _VT =              \
 313         {                                                                       \
 314                 .init = uart ## port ## _init,                                  \
 315                 .cleanup = uart ## port ## _cleanup,                            \
 316                 .setBaudrate = uart ## port ## _setbaudrate,                    \
 317                 .setParity = uart ## port ## _setparity,                        \
 318                 .txStart = uart ## port ## _txStart,                            \
 319                 .txSending = tx_sending,                                        \
 320         };
 321
 322 /* UART port instances */
 323 UART_PORT(0)
 324 UART_PORT(1)
 325 UART_PORT(2)
 326
 327 static struct CM3Serial UARTDesc[SER_CNT] =
 328 {
 329         {
 330                 .hw = {
 331                         .table = &UART0_VT,
 332                         .txbuffer = uart0_txbuffer,
 333                         .rxbuffer = uart0_rxbuffer,
 334                         .txbuffer_size = sizeof(uart0_txbuffer),
 335                         .rxbuffer_size = sizeof(uart0_rxbuffer),
 336                 },
 337                 .sending = false,
 338                 .base = UART0_BASE,
 339                 .irq = INT_UART0,
 340         },
 341         {
 342                 .hw = {
 343                         .table = &UART1_VT,
 344                         .txbuffer = uart1_txbuffer,
 345                         .rxbuffer = uart1_rxbuffer,
 346                         .txbuffer_size = sizeof(uart1_txbuffer),
 347                         .rxbuffer_size = sizeof(uart1_rxbuffer),
 348                 },
 349                 .sending = false,
 350                 .base = UART1_BASE,
 351                 .irq = INT_UART1,
 352         },
 353         {
 354                 .hw = {
 355                         .table = &UART2_VT,
 356                         .txbuffer = uart2_txbuffer,
 357                         .rxbuffer = uart2_rxbuffer,
 358                         .txbuffer_size = sizeof(uart2_txbuffer),
 359                         .rxbuffer_size = sizeof(uart2_rxbuffer),
 360                 },
 361                 .sending = false,
 362                 .base = UART2_BASE,
 363                 .irq = INT_UART2,
 364         },
 365 };
 366
 367 struct SerialHardware *ser_hw_getdesc(int port)
 368 {
 369         ASSERT(port >= 0 && port < SER_CNT);
 370         return &UARTDesc[port].hw;
 371 }