4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 UART interface driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/macros.h> /* for BV() */
39 #include <drv/gpio_lm3s.h>
40 #include <drv/ser_p.h>
42 #include <drv/irq_cm3.h>
43 #include "cfg/cfg_ser.h"
46 /* From the high-level serial driver */
47 extern struct Serial *ser_handles[SER_CNT];
51 struct SerialHardware hw;
57 /* Forward declaration */
58 static struct CM3Serial UARTDesc[SER_CNT];
60 /* GPIO descriptor for UART pins */
65 /* GPIO base address register */
71 /* Table to retrieve GPIO pins configuration to work as UART pins */
72 static const struct gpio_uart_info gpio_uart[SER_CNT] =
76 .base = GPIO_PORTA_BASE,
77 .pins = BV(1) | BV(0),
78 .sysctl = SYSCTL_RCGC2_GPIOA,
82 .base = GPIO_PORTD_BASE,
83 .pins = BV(3) | BV(2),
84 .sysctl = SYSCTL_RCGC2_GPIOD,
88 .base = GPIO_PORTG_BASE,
89 .pins = BV(1) | BV(0),
90 .sysctl = SYSCTL_RCGC2_GPIOG,
94 /* Clear the flags register */
95 INLINE void lm3s_uartClear(uint32_t base)
97 HWREG(base + UART_O_FR) = 0;
100 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud)
105 if (baud * 16 > CPU_FREQ)
110 div = (CPU_FREQ * 8 / baud + 1) / 2;
112 lm3s_uartDisable(base);
114 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
116 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
117 /* Set the baud rate */
118 HWREG(base + UART_O_IBRD) = div / 64;
119 HWREG(base + UART_O_FBRD) = div % 64;
120 lm3s_uartClear(base);
121 lm3s_uartEnable(base);
124 void lm3s_uartSetParity(uint32_t base, int parity)
126 /* Set 8-bit word, one stop bit by default */
127 uint32_t config = UART_LCRH_WLEN_8;
131 case SER_PARITY_NONE:
134 config |= UART_LCRH_PEN;
136 case SER_PARITY_EVEN:
137 config |= UART_LCRH_EPS | UART_LCRH_PEN;
143 lm3s_uartDisable(base);
144 HWREG(base + UART_O_LCRH) = config;
145 lm3s_uartClear(base);
146 lm3s_uartEnable(base);
149 void lm3s_uartInit(int port)
151 uint32_t reg_clock, base;
153 ASSERT(port >= 0 && port < SER_CNT);
155 base = UARTDesc[port].base;
156 reg_clock = 1 << port;
158 /* Enable the peripheral clock */
159 SYSCTL_RCGC1_R |= reg_clock;
160 SYSCTL_RCGC2_R |= gpio_uart[port].sysctl;
163 /* Configure GPIO pins to work as UART pins */
164 lm3s_gpioPinConfig(gpio_uart[port].base, gpio_uart[port].pins,
165 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
167 /* Set serial param: 115.200 bps, no parity */
168 lm3s_uartSetBaudRate(base, 115200);
169 lm3s_uartSetParity(base, SER_PARITY_NONE);
172 static bool tx_sending(struct SerialHardware *_hw)
174 struct CM3Serial *hw = (struct CM3Serial *)_hw;
178 static void uart_irq_rx(int port)
180 struct FIFOBuffer *rxfifo = &ser_handles[port]->rxfifo;
181 uint32_t base = UARTDesc[port].base;
184 while (lm3s_uartRxReady(base))
186 c = HWREG(base + UART_O_DR);
187 if (fifo_isfull(rxfifo))
188 ser_handles[port]->status |= SERRF_RXFIFOOVERRUN;
190 fifo_push(rxfifo, c);
194 static void uart_irq_tx(int port)
196 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;
197 uint32_t base = UARTDesc[port].base;
199 while (lm3s_uartTxReady(base))
201 if (fifo_isempty(txfifo)) {
203 * Disable TX empty interrupts if there're no more
204 * characters to transmit.
206 HWREG(base + UART_O_IM) &= ~UART_IM_TXIM;
207 UARTDesc[port].sending = false;
210 HWREG(base + UART_O_DR) = fifo_pop(txfifo);
214 static void uart_common_irq_handler(int port)
216 uint32_t base = UARTDesc[port].base;
219 /* Read and clear the IRQ status */
220 status = HWREG(base + UART_O_RIS);
222 /* Process the IRQ */
223 if (status & (UART_RIS_RXRIS | UART_RIS_RTRIS))
225 if (status & UART_RIS_TXRIS)
230 lm3s_uartIRQEnable(int port, sysirq_handler_t handler)
232 uint32_t base = UARTDesc[port].base;
233 sysirq_t irq = UARTDesc[port].irq;
235 /* Register the IRQ handler */
236 sysirq_setHandler(irq, handler);
237 /* Enable RX interrupt in the UART interrupt mask register */
238 HWREG(base + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM;
241 static void lm3s_uartIRQDisable(int port)
243 uint32_t base = UARTDesc[port].base;
245 HWREG(base + UART_O_IM) &=
246 ~(UART_IM_TXIM | UART_IM_RXIM | UART_IM_RTIM);
249 /* UART class definition */
250 #define UART_PORT(port) \
251 /* UART TX and RX buffers */ \
252 static unsigned char \
253 uart ## port ## _txbuffer[CONFIG_UART ## port ## _TXBUFSIZE]; \
254 static unsigned char \
255 uart ## port ## _rxbuffer[CONFIG_UART ## port ## _RXBUFSIZE]; \
257 /* UART interrupt handler */ \
258 static DECLARE_ISR(uart ## port ## _irq_handler) \
260 uart_common_irq_handler(port); \
263 /* UART public methods */ \
265 uart ## port ## _txStart(struct SerialHardware *_hw) \
267 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo; \
268 struct CM3Serial *hw = (struct CM3Serial *)_hw; \
272 lm3s_uartPutChar(UART ## port ## _BASE, fifo_pop(txfifo)); \
273 if (!fifo_isempty(txfifo)) \
275 HWREG(UART ## port ## _BASE + UART_O_IM) |= \
277 hw->sending = true; \
282 uart ## port ## _setbaudrate(UNUSED_ARG(struct SerialHardware *, hw), \
283 unsigned long baud) \
285 lm3s_uartSetBaudRate(UART ## port ## _BASE, baud); \
289 uart ## port ## _setparity(UNUSED_ARG(struct SerialHardware *, hw), \
292 lm3s_uartSetParity(UART ## port ## _BASE, parity); \
296 uart ## port ## _cleanup(struct SerialHardware *_hw) \
298 struct CM3Serial *hw = (struct CM3Serial *)_hw; \
300 hw->sending = false; \
301 lm3s_uartIRQDisable(port); \
302 lm3s_uartClear(UART ## port ## _BASE); \
303 lm3s_uartDisable(UART ## port ## _BASE); \
307 uart ## port ## _init(UNUSED_ARG(struct SerialHardware *, hw), \
308 UNUSED_ARG(struct Serial *, ser)) \
310 lm3s_uartInit(port); \
311 lm3s_uartEnable(UART ## port ## _BASE); \
312 lm3s_uartIRQEnable(port, uart ## port ## _irq_handler); \
315 /* UART operations */ \
316 static const struct SerialHardwareVT UART ## port ## _VT = \
318 .init = uart ## port ## _init, \
319 .cleanup = uart ## port ## _cleanup, \
320 .setBaudrate = uart ## port ## _setbaudrate, \
321 .setParity = uart ## port ## _setparity, \
322 .txStart = uart ## port ## _txStart, \
323 .txSending = tx_sending, \
326 /* UART port instances */
331 static struct CM3Serial UARTDesc[SER_CNT] =
336 .txbuffer = uart0_txbuffer,
337 .rxbuffer = uart0_rxbuffer,
338 .txbuffer_size = sizeof(uart0_txbuffer),
339 .rxbuffer_size = sizeof(uart0_rxbuffer),
348 .txbuffer = uart1_txbuffer,
349 .rxbuffer = uart1_rxbuffer,
350 .txbuffer_size = sizeof(uart1_txbuffer),
351 .rxbuffer_size = sizeof(uart1_rxbuffer),
360 .txbuffer = uart2_txbuffer,
361 .rxbuffer = uart2_rxbuffer,
362 .txbuffer_size = sizeof(uart2_txbuffer),
363 .rxbuffer_size = sizeof(uart2_rxbuffer),
371 struct SerialHardware *ser_hw_getdesc(int port)
373 ASSERT(port >= 0 && port < SER_CNT);
374 return &UARTDesc[port].hw;