4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 UART interface driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/macros.h> /* for BV() */
39 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
40 #include <drv/gpio_lm3s.h>
41 #include <drv/ser_p.h>
43 #include <drv/irq_cm3.h>
44 #include "cfg/cfg_ser.h"
47 /* From the high-level serial driver */
48 extern struct Serial *ser_handles[SER_CNT];
52 struct SerialHardware hw;
58 /* Forward declaration */
59 static struct CM3Serial UARTDesc[SER_CNT];
61 /* GPIO descriptor for UART pins */
64 /* GPIO base address register */
70 /* Table to retrieve GPIO pins configuration to work as UART pins */
71 static const struct gpio_uart_info gpio_uart[SER_CNT] =
75 .base = GPIO_PORTA_BASE,
76 .pins = BV(1) | BV(0),
80 .base = GPIO_PORTD_BASE,
81 .pins = BV(3) | BV(2),
85 .base = GPIO_PORTG_BASE,
86 .pins = BV(1) | BV(0),
90 /* Clear the flags register */
91 INLINE void lm3s_uartClear(uint32_t base)
93 HWREG(base + UART_O_FR) = 0;
96 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud)
101 if (baud * 16 > CPU_FREQ)
106 div = (CPU_FREQ * 8 / baud + 1) / 2;
108 lm3s_uartDisable(base);
110 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
112 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
113 /* Set the baud rate */
114 HWREG(base + UART_O_IBRD) = div / 64;
115 HWREG(base + UART_O_FBRD) = div % 64;
116 lm3s_uartClear(base);
117 lm3s_uartEnable(base);
120 void lm3s_uartSetParity(uint32_t base, int parity)
122 /* Set 8-bit word, one stop bit by default */
123 uint32_t config = UART_LCRH_WLEN_8;
127 case SER_PARITY_NONE:
130 config |= UART_LCRH_PEN;
132 case SER_PARITY_EVEN:
133 config |= UART_LCRH_EPS | UART_LCRH_PEN;
139 lm3s_uartDisable(base);
140 HWREG(base + UART_O_LCRH) = config;
141 lm3s_uartClear(base);
142 lm3s_uartEnable(base);
145 void lm3s_uartInit(int port)
147 uint32_t reg_clock, base;
149 ASSERT(port >= 0 && port < SER_CNT);
151 base = UARTDesc[port].base;
152 reg_clock = 1 << port;
154 /* Enable the peripheral clock */
155 SYSCTL_RCGC1_R |= reg_clock;
156 SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
159 /* Configure GPIO pins to work as UART pins */
160 lm3s_gpioPinConfig(gpio_uart[port].base, gpio_uart[port].pins,
161 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
163 /* Set serial param: 115.200 bps, no parity */
164 lm3s_uartSetBaudRate(base, 115200);
165 lm3s_uartSetParity(base, SER_PARITY_NONE);
168 static bool tx_sending(struct SerialHardware *_hw)
170 struct CM3Serial *hw = (struct CM3Serial *)_hw;
174 static void uart_irq_rx(int port)
176 struct FIFOBuffer *rxfifo = &ser_handles[port]->rxfifo;
177 uint32_t base = UARTDesc[port].base;
180 while (lm3s_uartRxReady(base))
182 c = HWREG(base + UART_O_DR);
183 if (fifo_isfull(rxfifo))
184 ser_handles[port]->status |= SERRF_RXFIFOOVERRUN;
186 fifo_push(rxfifo, c);
190 static void uart_irq_tx(int port)
192 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;
193 uint32_t base = UARTDesc[port].base;
195 while (lm3s_uartTxReady(base))
197 if (fifo_isempty(txfifo)) {
199 * Disable TX empty interrupts if there're no more
200 * characters to transmit.
202 HWREG(base + UART_O_IM) &= ~UART_IM_TXIM;
203 UARTDesc[port].sending = false;
206 HWREG(base + UART_O_DR) = fifo_pop(txfifo);
210 static void uart_common_irq_handler(int port)
212 uint32_t base = UARTDesc[port].base;
215 /* Read and clear the IRQ status */
216 status = HWREG(base + UART_O_RIS);
218 /* Process the IRQ */
219 if (status & (UART_RIS_RXRIS | UART_RIS_RTRIS))
221 if (status & UART_RIS_TXRIS)
226 lm3s_uartIRQEnable(int port, sysirq_handler_t handler)
228 uint32_t base = UARTDesc[port].base;
229 sysirq_t irq = UARTDesc[port].irq;
231 /* Register the IRQ handler */
232 sysirq_setHandler(irq, handler);
233 /* Enable RX interrupt in the UART interrupt mask register */
234 HWREG(base + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM;
237 static void lm3s_uartIRQDisable(int port)
239 uint32_t base = UARTDesc[port].base;
241 HWREG(base + UART_O_IM) &=
242 ~(UART_IM_TXIM | UART_IM_RXIM | UART_IM_RTIM);
245 /* UART class definition */
246 #define UART_PORT(port) \
247 /* UART TX and RX buffers */ \
248 static unsigned char \
249 uart ## port ## _txbuffer[CONFIG_UART ## port ## _TXBUFSIZE]; \
250 static unsigned char \
251 uart ## port ## _rxbuffer[CONFIG_UART ## port ## _RXBUFSIZE]; \
253 /* UART interrupt handler */ \
254 static DECLARE_ISR(uart ## port ## _irq_handler) \
256 uart_common_irq_handler(port); \
259 /* UART public methods */ \
261 uart ## port ## _txStart(struct SerialHardware *_hw) \
263 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo; \
264 struct CM3Serial *hw = (struct CM3Serial *)_hw; \
268 lm3s_uartPutChar(UART ## port ## _BASE, fifo_pop(txfifo)); \
269 if (!fifo_isempty(txfifo)) \
271 HWREG(UART ## port ## _BASE + UART_O_IM) |= \
273 hw->sending = true; \
278 uart ## port ## _setbaudrate(UNUSED_ARG(struct SerialHardware *, hw), \
279 unsigned long baud) \
281 lm3s_uartSetBaudRate(UART ## port ## _BASE, baud); \
285 uart ## port ## _setparity(UNUSED_ARG(struct SerialHardware *, hw), \
288 lm3s_uartSetParity(UART ## port ## _BASE, parity); \
292 uart ## port ## _cleanup(struct SerialHardware *_hw) \
294 struct CM3Serial *hw = (struct CM3Serial *)_hw; \
296 hw->sending = false; \
297 lm3s_uartIRQDisable(port); \
298 lm3s_uartClear(UART ## port ## _BASE); \
299 lm3s_uartDisable(UART ## port ## _BASE); \
303 uart ## port ## _init(UNUSED_ARG(struct SerialHardware *, hw), \
304 UNUSED_ARG(struct Serial *, ser)) \
306 lm3s_uartInit(port); \
307 lm3s_uartEnable(UART ## port ## _BASE); \
308 lm3s_uartIRQEnable(port, uart ## port ## _irq_handler); \
311 /* UART operations */ \
312 static const struct SerialHardwareVT UART ## port ## _VT = \
314 .init = uart ## port ## _init, \
315 .cleanup = uart ## port ## _cleanup, \
316 .setBaudrate = uart ## port ## _setbaudrate, \
317 .setParity = uart ## port ## _setparity, \
318 .txStart = uart ## port ## _txStart, \
319 .txSending = tx_sending, \
322 /* UART port instances */
327 static struct CM3Serial UARTDesc[SER_CNT] =
332 .txbuffer = uart0_txbuffer,
333 .rxbuffer = uart0_rxbuffer,
334 .txbuffer_size = sizeof(uart0_txbuffer),
335 .rxbuffer_size = sizeof(uart0_rxbuffer),
344 .txbuffer = uart1_txbuffer,
345 .rxbuffer = uart1_rxbuffer,
346 .txbuffer_size = sizeof(uart1_txbuffer),
347 .rxbuffer_size = sizeof(uart1_rxbuffer),
356 .txbuffer = uart2_txbuffer,
357 .rxbuffer = uart2_rxbuffer,
358 .txbuffer_size = sizeof(uart2_txbuffer),
359 .rxbuffer_size = sizeof(uart2_rxbuffer),
367 struct SerialHardware *ser_hw_getdesc(int port)
369 ASSERT(port >= 0 && port < SER_CNT);
370 return &UARTDesc[port].hw;