bertos/cpu/cortex-m3/drv/ser_lm3s.c

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  29  * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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  32  *
  33  * \brief LM3S1968 UART interface driver.
  34  *
  35  * \author Andrea Righi <arighi@develer.com>
  36  */
  37
  38 #include <cfg/macros.h> /* for BV() */
  39 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
  40 #include <drv/gpio_lm3s.h>
  41 #include <drv/ser_p.h>
  42 #include <drv/ser.h>
  43 #include <drv/irq_cm3.h>
  44 #include "cfg/cfg_ser.h"
  45 #include "ser_lm3s.h"
  46
  47 /* From the high-level serial driver */
  48 extern struct Serial *ser_handles[SER_CNT];
  49
  50 struct CM3Serial
  51 {
  52         struct SerialHardware hw;
  53         bool sending;
  54         uint32_t base;
  55         sysirq_t irq;
  56 };
  57
  58 /* Forward declaration */
  59 static struct CM3Serial UARTDesc[SER_CNT];
  60
  61 /* GPIO descriptor for UART pins */
  62 struct gpio_uart_info
  63 {
  64         /* Sysctl */
  65         uint32_t sysctl;
  66         /* GPIO base address register */
  67         uint32_t base;
  68         /* Pin(s) bitmask */
  69         uint8_t pins;
  70 };
  71
  72 /* Table to retrieve GPIO pins configuration to work as UART pins */
  73 static const struct gpio_uart_info gpio_uart[SER_CNT] =
  74 {
  75         /* UART0 */
  76         {
  77                 .base = GPIO_PORTA_BASE,
  78                 .pins = BV(1) | BV(0),
  79                 .sysctl = SYSCTL_RCGC2_GPIOA,
  80         },
  81         /* UART1 */
  82         {
  83                 .base = GPIO_PORTD_BASE,
  84                 .pins = BV(3) | BV(2),
  85                 .sysctl = SYSCTL_RCGC2_GPIOD,
  86         },
  87         /* UART2 */
  88         {
  89                 .base = GPIO_PORTG_BASE,
  90                 .pins = BV(1) | BV(0),
  91                 .sysctl = SYSCTL_RCGC2_GPIOG,
  92         },
  93 };
  94
  95 /* Clear the flags register */
  96 INLINE void lm3s_uartClear(uint32_t base)
  97 {
  98         HWREG(base + UART_O_FR) = 0;
  99 }
 100
 101 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud)
 102 {
 103         unsigned long div;
 104         bool hi_speed;
 105
 106         if (baud * 16 > CPU_FREQ)
 107         {
 108                 hi_speed = true;
 109                 baud /= 2;
 110         }
 111         div = (CPU_FREQ * 8 / baud + 1) / 2;
 112
 113         lm3s_uartDisable(base);
 114         if (hi_speed)
 115                 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
 116         else
 117                 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
 118         /* Set the baud rate */
 119         HWREG(base + UART_O_IBRD) = div / 64;
 120         HWREG(base + UART_O_FBRD) = div % 64;
 121         lm3s_uartClear(base);
 122         lm3s_uartEnable(base);
 123 }
 124
 125 void lm3s_uartSetParity(uint32_t base, int parity)
 126 {
 127         /* Set 8-bit word, one stop bit by default */
 128         uint32_t config = UART_LCRH_WLEN_8;
 129
 130         switch(parity)
 131         {
 132         case SER_PARITY_NONE:
 133                 break;
 134         case SER_PARITY_ODD:
 135                 config |= UART_LCRH_PEN;
 136                 break;
 137         case SER_PARITY_EVEN:
 138                 config |= UART_LCRH_EPS | UART_LCRH_PEN;
 139                 break;
 140         default:
 141                 ASSERT(0);
 142                 return;
 143         }
 144         lm3s_uartDisable(base);
 145         HWREG(base + UART_O_LCRH) = config;
 146         lm3s_uartClear(base);
 147         lm3s_uartEnable(base);
 148 }
 149
 150 void lm3s_uartInit(int port)
 151 {
 152         uint32_t reg_clock, base;
 153
 154         ASSERT(port >= 0 && port < SER_CNT);
 155
 156         base = UARTDesc[port].base;
 157         reg_clock = 1 << port;
 158
 159         /* Enable the peripheral clock */
 160         SYSCTL_RCGC1_R |= reg_clock;
 161         SYSCTL_RCGC2_R |= gpio_uart[port].sysctl;
 162         lm3s_busyWait(512);
 163
 164         /* Configure GPIO pins to work as UART pins */
 165         lm3s_gpioPinConfig(gpio_uart[port].base, gpio_uart[port].pins,
 166                         GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 167
 168         /* Set serial param: 115.200 bps, no parity */
 169         lm3s_uartSetBaudRate(base, 115200);
 170         lm3s_uartSetParity(base, SER_PARITY_NONE);
 171 }
 172
 173 static bool tx_sending(struct SerialHardware *_hw)
 174 {
 175         struct CM3Serial *hw = (struct CM3Serial *)_hw;
 176         return hw->sending;
 177 }
 178
 179 static void uart_irq_rx(int port)
 180 {
 181         struct FIFOBuffer *rxfifo = &ser_handles[port]->rxfifo;
 182         uint32_t base = UARTDesc[port].base;
 183         char c;
 184
 185         while (lm3s_uartRxReady(base))
 186         {
 187                 c = HWREG(base + UART_O_DR);
 188                 if (fifo_isfull(rxfifo))
 189                         ser_handles[port]->status |= SERRF_RXFIFOOVERRUN;
 190                 else
 191                         fifo_push(rxfifo, c);
 192         }
 193 }
 194
 195 static void uart_irq_tx(int port)
 196 {
 197         struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;
 198         uint32_t base = UARTDesc[port].base;
 199
 200         while (lm3s_uartTxReady(base))
 201         {
 202                 if (fifo_isempty(txfifo)) {
 203                         /*
 204                          * Disable TX empty interrupts if there're no more
 205                          * characters to transmit.
 206                          */
 207                         HWREG(base + UART_O_IM) &= ~UART_IM_TXIM;
 208                         UARTDesc[port].sending = false;
 209                         break;
 210                 }
 211                 HWREG(base + UART_O_DR) = fifo_pop(txfifo);
 212         }
 213 }
 214
 215 static void uart_common_irq_handler(int port)
 216 {
 217         uint32_t base = UARTDesc[port].base;
 218         uint32_t status;
 219
 220         /* Read and clear the IRQ status */
 221         status = HWREG(base + UART_O_RIS);
 222
 223         /* Process the IRQ */
 224         if (status & (UART_RIS_RXRIS | UART_RIS_RTRIS))
 225                 uart_irq_rx(port);
 226         if (status & UART_RIS_TXRIS)
 227                 uart_irq_tx(port);
 228 }
 229
 230 static void
 231 lm3s_uartIRQEnable(int port, sysirq_handler_t handler)
 232 {
 233         uint32_t base = UARTDesc[port].base;
 234         sysirq_t irq = UARTDesc[port].irq;
 235
 236         /* Register the IRQ handler */
 237         sysirq_setHandler(irq, handler);
 238         /* Enable RX interrupt in the UART interrupt mask register */
 239         HWREG(base + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM;
 240 }
 241
 242 static void lm3s_uartIRQDisable(int port)
 243 {
 244         uint32_t base = UARTDesc[port].base;
 245
 246         HWREG(base + UART_O_IM) &=
 247                         ~(UART_IM_TXIM | UART_IM_RXIM | UART_IM_RTIM);
 248 }
 249
 250 /* UART class definition */
 251 #define UART_PORT(port)                                                         \
 252         /* UART TX and RX buffers */                                            \
 253         static unsigned char                                                    \
 254                 uart ## port ## _txbuffer[CONFIG_UART ## port ## _TXBUFSIZE];   \
 255         static unsigned char                                                    \
 256                 uart ## port ## _rxbuffer[CONFIG_UART ## port ## _RXBUFSIZE];   \
 257                                                                                 \
 258         /* UART interrupt handler */                                            \
 259         static DECLARE_ISR(uart ## port ## _irq_handler)                        \
 260         {                                                                       \
 261                 uart_common_irq_handler(port);                                  \
 262         }                                                                       \
 263                                                                                 \
 264         /* UART public methods */                                               \
 265         static void                                                             \
 266         uart ## port ## _txStart(struct SerialHardware *_hw)                    \
 267         {                                                                       \
 268                 struct FIFOBuffer *txfifo = &ser_handles[port]->txfifo;         \
 269                 struct CM3Serial *hw = (struct CM3Serial *)_hw;                 \
 270                                                                                 \
 271                 if (hw->sending)                                                \
 272                         return;                                                 \
 273                 lm3s_uartPutChar(UART ## port ## _BASE, fifo_pop(txfifo));      \
 274                 if (!fifo_isempty(txfifo))                                      \
 275                 {                                                               \
 276                         HWREG(UART ## port ## _BASE + UART_O_IM) |=             \
 277                                                  UART_IM_TXIM;                  \
 278                         hw->sending = true;                                     \
 279                 }                                                               \
 280         }                                                                       \
 281                                                                                 \
 282         static void                                                             \
 283         uart ## port ## _setbaudrate(UNUSED_ARG(struct SerialHardware *, hw),   \
 284                                                 unsigned long baud)             \
 285         {                                                                       \
 286                 lm3s_uartSetBaudRate(UART ## port ## _BASE, baud);              \
 287         }                                                                       \
 288                                                                                 \
 289         static void                                                             \
 290         uart ## port ## _setparity(UNUSED_ARG(struct SerialHardware *, hw),     \
 291                                                 int parity)                     \
 292         {                                                                       \
 293                 lm3s_uartSetParity(UART ## port ## _BASE, parity);              \
 294         }                                                                       \
 295                                                                                 \
 296         static void                                                             \
 297         uart ## port ## _cleanup(struct SerialHardware *_hw)                    \
 298         {                                                                       \
 299                 struct CM3Serial *hw = (struct CM3Serial *)_hw;                 \
 300                                                                                 \
 301                 hw->sending = false;                                            \
 302                 lm3s_uartIRQDisable(port);                                      \
 303                 lm3s_uartClear(UART ## port ## _BASE);                          \
 304                 lm3s_uartDisable(UART ## port ## _BASE);                        \
 305         }                                                                       \
 306                                                                                 \
 307         static void                                                             \
 308         uart ## port ## _init(UNUSED_ARG(struct SerialHardware *, hw),          \
 309                                 UNUSED_ARG(struct Serial *, ser))               \
 310         {                                                                       \
 311                 lm3s_uartInit(port);                                            \
 312                 lm3s_uartEnable(UART ## port ## _BASE);                         \
 313                 lm3s_uartIRQEnable(port, uart ## port ## _irq_handler);         \
 314         }                                                                       \
 315                                                                                 \
 316         /* UART operations */                                                   \
 317         static const struct SerialHardwareVT UART ## port ## _VT =              \
 318         {                                                                       \
 319                 .init = uart ## port ## _init,                                  \
 320                 .cleanup = uart ## port ## _cleanup,                            \
 321                 .setBaudrate = uart ## port ## _setbaudrate,                    \
 322                 .setParity = uart ## port ## _setparity,                        \
 323                 .txStart = uart ## port ## _txStart,                            \
 324                 .txSending = tx_sending,                                        \
 325         };
 326
 327 /* UART port instances */
 328 UART_PORT(0)
 329 UART_PORT(1)
 330 UART_PORT(2)
 331
 332 static struct CM3Serial UARTDesc[SER_CNT] =
 333 {
 334         {
 335                 .hw = {
 336                         .table = &UART0_VT,
 337                         .txbuffer = uart0_txbuffer,
 338                         .rxbuffer = uart0_rxbuffer,
 339                         .txbuffer_size = sizeof(uart0_txbuffer),
 340                         .rxbuffer_size = sizeof(uart0_rxbuffer),
 341                 },
 342                 .sending = false,
 343                 .base = UART0_BASE,
 344                 .irq = INT_UART0,
 345         },
 346         {
 347                 .hw = {
 348                         .table = &UART1_VT,
 349                         .txbuffer = uart1_txbuffer,
 350                         .rxbuffer = uart1_rxbuffer,
 351                         .txbuffer_size = sizeof(uart1_txbuffer),
 352                         .rxbuffer_size = sizeof(uart1_rxbuffer),
 353                 },
 354                 .sending = false,
 355                 .base = UART1_BASE,
 356                 .irq = INT_UART1,
 357         },
 358         {
 359                 .hw = {
 360                         .table = &UART2_VT,
 361                         .txbuffer = uart2_txbuffer,
 362                         .rxbuffer = uart2_rxbuffer,
 363                         .txbuffer_size = sizeof(uart2_txbuffer),
 364                         .rxbuffer_size = sizeof(uart2_rxbuffer),
 365                 },
 366                 .sending = false,
 367                 .base = UART2_BASE,
 368                 .irq = INT_UART2,
 369         },
 370 };
 371
 372 struct SerialHardware *ser_hw_getdesc(int port)
 373 {
 374         ASSERT(port >= 0 && port < SER_CNT);
 375         return &UARTDesc[port].hw;
 376 }