4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \author Daniele Basile <asterix@develer.com>
40 #include "hw/hw_ser.h" /* Required for bus macros overrides */
41 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
43 #include "cfg/cfg_ser.h"
44 #include <cfg/debug.h>
49 #include <drv/irq_cm3.h>
54 #include <drv/ser_p.h>
56 #include <struct/fifobuf.h>
59 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
62 * \name Overridable serial bus hooks
64 * These can be redefined in hw.h to implement
65 * special bus policies such as half-duplex, 485, etc.
69 * TXBEGIN TXCHAR TXEND TXOFF
70 * | __________|__________ | |
73 * ______ __ __ __ __ __ __ ________________
74 * \/ \/ \/ \/ \/ \/ \/
75 * ______/\__/\__/\__/\__/\__/\__/
82 #ifndef SER_UART0_BUS_TXINIT
84 * Default TXINIT macro - invoked in uart0_init()
86 * - Disable GPIO on USART0 tx/rx pins
88 #if CPU_ARM_AT91 && !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
89 #warning Check USART0 pins!
91 #define SER_UART0_BUS_TXINIT do { \
92 PIOA_PDR = BV(RXD0) | BV(TXD0); \
96 #ifndef SER_UART0_BUS_TXBEGIN
98 * Invoked before starting a transmission
100 #define SER_UART0_BUS_TXBEGIN
103 #ifndef SER_UART0_BUS_TXCHAR
105 * Invoked to send one character.
107 #define SER_UART0_BUS_TXCHAR(c) do { \
112 #ifndef SER_UART0_BUS_TXEND
114 * Invoked as soon as the txfifo becomes empty
116 #define SER_UART0_BUS_TXEND
119 /* End USART0 macros */
121 #if !CPU_CM3_AT91SAM3U
123 #ifndef SER_UART1_BUS_TXINIT
125 * Default TXINIT macro - invoked in uart1_init()
127 * - Disable GPIO on USART1 tx/rx pins
130 #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
131 #warning Check USART1 pins!
133 #define SER_UART1_BUS_TXINIT do { \
134 PIOA_PDR = BV(RXD1) | BV(TXD1); \
136 #elif CPU_CM3_AT91SAM3
137 #define SER_UART1_BUS_TXINIT do { \
138 PIOB_PDR = BV(RXD1) | BV(TXD1); \
145 #ifndef SER_UART1_BUS_TXBEGIN
147 * Invoked before starting a transmission
149 #define SER_UART1_BUS_TXBEGIN
152 #ifndef SER_UART1_BUS_TXCHAR
154 * Invoked to send one character.
156 #define SER_UART1_BUS_TXCHAR(c) do { \
161 #ifndef SER_UART1_BUS_TXEND
163 * Invoked as soon as the txfifo becomes empty
165 #define SER_UART1_BUS_TXEND
171 * \name Overridable SPI hooks
173 * These can be redefined in hw.h to implement
174 * special bus policies such as slave select pin handling, etc.
179 #ifndef SER_SPI0_BUS_TXINIT
181 * Default TXINIT macro - invoked in spi_init()
182 * The default is no action.
185 #define SER_SPI0_BUS_TXINIT do { \
186 /* Disable PIO on SPI pins */ \
187 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO) | BV(30); \
188 /* PIO is peripheral A */ \
189 PIOA_ABCDSR1 &= ~(BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO)); \
190 PIOA_ABCDSR2 &= ~(BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO)); \
191 /* Peripheral B for chip select for display */ \
192 PIOA_ABCDSR1 |= BV(30); \
193 PIOA_ABCDSR2 &= ~BV(30); \
196 #define SER_SPI0_BUS_TXINIT do { \
197 /* Disable PIO on SPI pins */ \
198 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
203 #ifndef SER_SPI0_BUS_TXCLOSE
205 * Invoked after the last character has been transmitted.
206 * The default is no action.
208 #define SER_SPI0_BUS_TXCLOSE do { \
209 /* Enable PIO on SPI pins */ \
210 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
216 #ifndef SER_SPI1_BUS_TXINIT
218 * Default TXINIT macro - invoked in spi_init()
219 * The default is no action.
221 #define SER_SPI1_BUS_TXINIT do { \
222 /* Disable PIO on SPI pins */ \
223 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
224 /* SPI1 pins are on B peripheral function! */ \
225 PIOA_BSR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
229 #ifndef SER_SPI1_BUS_TXCLOSE
231 * Invoked after the last character has been transmitted.
232 * The default is no action.
234 #define SER_SPI1_BUS_TXCLOSE do { \
235 /* Enable PIO on SPI pins */ \
236 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
244 * \name Core dependent interrupt handling macros
246 * Atmel serial hardware is used on different CPU cores,
247 * i.e. SAM3 and SAM7. The user interface of the serial
248 * subsystem is identical but core interrupt controllers
255 INLINE void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler)
257 /* Set the vector. */
258 AIC_SVR(irq) = uart0_irq_dispatcher;
260 /* Initialize to level/edge sensitive with defined priority. */
262 if (irq == SPI0_ID || irq == SPI1_ID)
266 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_SRCTYPE_MASK) | AIC_SRCTYPE_INT_EDGE_TRIGGERED;
268 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_SRCTYPE_MASK) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE;
274 INLINE void sysirq_setPriority(sysirq_t irq, int prio)
276 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_PRIOR_MASK) | SERIRQ_PRIORITY;
279 /** Inform hw that we have served the IRQ */
280 #define SER_INT_ACK do { \
284 #elif CPU_CM3_AT91SAM3
286 /** Inform hw that we have served the IRQ */
287 #define SER_INT_ACK do { /* nop */ } while (0)
290 #error No interrupt handling macros defined for current architecture
295 /* From the high-level serial driver */
296 extern struct Serial *ser_handles[SER_CNT];
298 /* TX and RX buffers */
299 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
300 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
301 #if !CPU_CM3_AT91SAM3U
302 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
303 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
305 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
306 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
308 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
309 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
313 * Internal hardware state structure
315 * The \a sending variable is true while the transmission
316 * interrupt is retriggering itself.
318 * For the USARTs the \a sending flag is useful for taking specific
319 * actions before sending a burst of data, at the start of a trasmission
320 * but not before every char sent.
322 * For the SPI, this flag is necessary because the SPI sends and receives
323 * bytes at the same time and the SPI IRQ is unique for send/receive.
324 * The only way to start transmission is to write data in SPDR (this
325 * is done by spi_starttx()). We do this *only* if a transfer is
326 * not already started.
330 struct SerialHardware hw;
331 volatile bool sending;
334 static ISR_PROTO(uart0_irq_dispatcher);
335 #if !CPU_CM3_AT91SAM3U
336 static ISR_PROTO(uart1_irq_dispatcher);
338 static ISR_PROTO(spi0_irq_handler);
340 static ISR_PROTO(spi1_irq_handler);
343 * Callbacks for USART0
345 static void uart0_init(
346 UNUSED_ARG(struct SerialHardware *, _hw),
347 UNUSED_ARG(struct Serial *, ser))
349 US0_IDR = 0xFFFFFFFF;
350 PMC_PCER = BV(US0_ID);
354 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
355 * - Enable both the receiver and the transmitter
356 * - Enable only the RX complete interrupt
358 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
359 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
360 US0_CR = BV(US_RXEN) | BV(US_TXEN);
361 US0_IER = BV(US_RXRDY);
363 SER_UART0_BUS_TXINIT;
365 sysirq_setPriority(INT_US0, SERIRQ_PRIORITY);
366 sysirq_setHandler(INT_US0, uart0_irq_dispatcher);
371 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
373 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
376 static void uart0_enabletxirq(struct SerialHardware *_hw)
378 struct ArmSerial *hw = (struct ArmSerial *)_hw;
381 * WARNING: racy code here! The tx interrupt sets hw->sending to false
382 * when it runs with an empty fifo. The order of statements in the
389 * - Enable the transmitter
390 * - Enable TX empty interrupt
392 SER_UART0_BUS_TXBEGIN;
393 US0_IER = BV(US_TXEMPTY);
397 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
399 /* Compute baud-rate period */
400 US0_BRGR = CPU_FREQ / (16 * rate);
401 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
404 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
406 US0_MR &= ~US_PAR_MASK;
407 /* Set UART parity */
410 case SER_PARITY_NONE:
416 case SER_PARITY_EVEN:
419 US0_MR |= US_PAR_EVEN;
425 US0_MR |= US_PAR_ODD;
433 * Callbacks for USART1
435 static void uart1_init(
436 UNUSED_ARG(struct SerialHardware *, _hw),
437 UNUSED_ARG(struct Serial *, ser))
439 US1_IDR = 0xFFFFFFFF;
440 PMC_PCER = BV(US1_ID);
444 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
445 * - Enable both the receiver and the transmitter
446 * - Enable only the RX complete interrupt
448 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
449 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
450 US1_CR = BV(US_RXEN) | BV(US_TXEN);
451 US1_IER = BV(US_RXRDY);
453 SER_UART1_BUS_TXINIT;
455 sysirq_setPriority(INT_US1, SERIRQ_PRIORITY);
456 sysirq_setHandler(INT_US1, uart1_irq_dispatcher);
461 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
463 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
466 static void uart1_enabletxirq(struct SerialHardware *_hw)
468 struct ArmSerial *hw = (struct ArmSerial *)_hw;
471 * WARNING: racy code here! The tx interrupt sets hw->sending to false
472 * when it runs with an empty fifo. The order of statements in the
479 * - Enable the transmitter
480 * - Enable TX empty interrupt
482 SER_UART1_BUS_TXBEGIN;
483 US1_IER = BV(US_TXEMPTY);
487 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
489 /* Compute baud-rate period */
490 US1_BRGR = CPU_FREQ / (16 * rate);
491 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
494 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
496 US1_MR &= ~US_PAR_MASK;
497 /* Set UART parity */
500 case SER_PARITY_NONE:
506 case SER_PARITY_EVEN:
509 US1_MR |= US_PAR_EVEN;
515 US1_MR |= US_PAR_ODD;
524 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
529 SPI0_CR = BV(SPI_SWRST);
532 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
533 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
535 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); // | SPI_PCS_2;
539 * At reset clock division factor is set to 0, that is
540 * *forbidden*. Set SPI clock to minimum to keep it valid.
542 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
544 /* Disable all irqs */
545 SPI0_IDR = 0xFFFFFFFF;
547 //sysirq_setPriority(INT_SPI0, SERIRQ_PRIORITY);
548 sysirq_setHandler(INT_SPI0, spi0_irq_handler);
549 PMC_PCER = BV(SPI0_ID);
551 /* Enable interrupt on tx buffer empty */
552 SPI0_IER = BV(SPI_TXEMPTY);
555 SPI0_CR = BV(SPI_SPIEN);
560 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
563 SPI0_CR = BV(SPI_SPIDIS);
565 /* Disable all irqs */
566 SPI0_IDR = 0xFFFFFFFF;
568 SER_SPI0_BUS_TXCLOSE;
571 static void spi0_starttx(struct SerialHardware *_hw)
573 struct ArmSerial *hw = (struct ArmSerial *)_hw;
576 IRQ_SAVE_DISABLE(flags);
578 /* Send data only if the SPI is not already transmitting */
579 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
582 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
588 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
590 SPI0_CSR0 &= ~SPI_SCBR;
592 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
593 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
598 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
603 SPI1_CR = BV(SPI_SWRST);
606 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
607 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
609 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
613 * At reset clock division factor is set to 0, that is
614 * *forbidden*. Set SPI clock to minimum to keep it valid.
616 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
618 /* Disable all SPI irqs */
619 SPI1_IDR = 0xFFFFFFFF;
621 sysirq_setPriority(INT_SPI1, SERIRQ_PRIORITY);
622 sysirq_setHandler(INT_SPI1, spi1_irq_dispatcher);
623 PMC_PCER = BV(SPI1_ID);
625 /* Enable interrupt on tx buffer empty */
626 SPI1_IER = BV(SPI_TXEMPTY);
629 SPI1_CR = BV(SPI_SPIEN);
634 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
637 SPI1_CR = BV(SPI_SPIDIS);
639 /* Disable all irqs */
640 SPI1_IDR = 0xFFFFFFFF;
642 SER_SPI1_BUS_TXCLOSE;
645 static void spi1_starttx(struct SerialHardware *_hw)
647 struct ArmSerial *hw = (struct ArmSerial *)_hw;
650 IRQ_SAVE_DISABLE(flags);
652 /* Send data only if the SPI is not already transmitting */
653 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
656 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
662 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
664 SPI1_CSR0 &= ~SPI_SCBR;
666 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
667 SPI1_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
671 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
677 static bool tx_sending(struct SerialHardware* _hw)
679 struct ArmSerial *hw = (struct ArmSerial *)_hw;
683 // FIXME: move into compiler.h? Ditch?
685 #define C99INIT(name,val) .name = val
686 #elif defined(__GNUC__)
687 #define C99INIT(name,val) name: val
689 #warning No designated initializers, double check your code
690 #define C99INIT(name,val) (val)
694 * High-level interface data structures
696 static const struct SerialHardwareVT UART0_VT =
698 C99INIT(init, uart0_init),
699 C99INIT(cleanup, uart0_cleanup),
700 C99INIT(setBaudrate, uart0_setbaudrate),
701 C99INIT(setParity, uart0_setparity),
702 C99INIT(txStart, uart0_enabletxirq),
703 C99INIT(txSending, tx_sending),
706 static const struct SerialHardwareVT UART1_VT =
708 C99INIT(init, uart1_init),
709 C99INIT(cleanup, uart1_cleanup),
710 C99INIT(setBaudrate, uart1_setbaudrate),
711 C99INIT(setParity, uart1_setparity),
712 C99INIT(txStart, uart1_enabletxirq),
713 C99INIT(txSending, tx_sending),
716 static const struct SerialHardwareVT SPI0_VT =
718 C99INIT(init, spi0_init),
719 C99INIT(cleanup, spi0_cleanup),
720 C99INIT(setBaudrate, spi0_setbaudrate),
721 C99INIT(setParity, spi_setparity),
722 C99INIT(txStart, spi0_starttx),
723 C99INIT(txSending, tx_sending),
726 static const struct SerialHardwareVT SPI1_VT =
728 C99INIT(init, spi1_init),
729 C99INIT(cleanup, spi1_cleanup),
730 C99INIT(setBaudrate, spi1_setbaudrate),
731 C99INIT(setParity, spi_setparity),
732 C99INIT(txStart, spi1_starttx),
733 C99INIT(txSending, tx_sending),
737 static struct ArmSerial UARTDescs[SER_CNT] =
741 C99INIT(table, &UART0_VT),
742 C99INIT(txbuffer, uart0_txbuffer),
743 C99INIT(rxbuffer, uart0_rxbuffer),
744 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
745 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
747 C99INIT(sending, false),
751 C99INIT(table, &UART1_VT),
752 C99INIT(txbuffer, uart1_txbuffer),
753 C99INIT(rxbuffer, uart1_rxbuffer),
754 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
755 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
757 C99INIT(sending, false),
762 C99INIT(table, &SPI0_VT),
763 C99INIT(txbuffer, spi0_txbuffer),
764 C99INIT(rxbuffer, spi0_rxbuffer),
765 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
766 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
768 C99INIT(sending, false),
773 C99INIT(table, &SPI1_VT),
774 C99INIT(txbuffer, spi1_txbuffer),
775 C99INIT(rxbuffer, spi1_rxbuffer),
776 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
777 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
779 C99INIT(sending, false),
785 struct SerialHardware *ser_hw_getdesc(int unit)
787 ASSERT(unit < SER_CNT);
788 return &UARTDescs[unit].hw;
792 * Serial 0 TX interrupt handler
794 INLINE void uart0_irq_tx(void)
798 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
800 if (fifo_isempty(txfifo))
803 * - Disable the TX empty interrupts
805 US0_IDR = BV(US_TXEMPTY);
807 UARTDescs[SER_UART0].sending = false;
811 char c = fifo_pop(txfifo);
812 SER_UART0_BUS_TXCHAR(c);
819 * Serial 0 RX complete interrupt handler.
821 INLINE void uart0_irq_rx(void)
825 /* Should be read before US_CRS */
826 ser_handles[SER_UART0]->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
827 US0_CR = BV(US_RSTSTA);
830 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
832 if (fifo_isfull(rxfifo))
833 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
835 fifo_push(rxfifo, c);
841 * Serial IRQ dispatcher for USART0.
843 static DECLARE_ISR(uart0_irq_dispatcher)
845 if (US0_CSR & BV(US_RXRDY))
848 if (US0_CSR & BV(US_TXEMPTY))
855 * Serial 1 TX interrupt handler
857 INLINE void uart1_irq_tx(void)
861 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
863 if (fifo_isempty(txfifo))
866 * - Disable the TX empty interrupts
868 US1_IDR = BV(US_TXEMPTY);
870 UARTDescs[SER_UART1].sending = false;
874 char c = fifo_pop(txfifo);
875 SER_UART1_BUS_TXCHAR(c);
882 * Serial 1 RX complete interrupt handler.
884 INLINE void uart1_irq_rx(void)
888 /* Should be read before US_CRS */
889 ser_handles[SER_UART1]->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
890 US1_CR = BV(US_RSTSTA);
893 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
895 if (fifo_isfull(rxfifo))
896 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
898 fifo_push(rxfifo, c);
904 * Serial IRQ dispatcher for USART1.
906 static DECLARE_ISR(uart1_irq_dispatcher)
908 if (US1_CSR & BV(US_RXRDY))
911 if (US1_CSR & BV(US_TXEMPTY))
918 * SPI0 interrupt handler
920 static DECLARE_ISR(spi0_irq_handler)
925 /* Read incoming byte. */
926 if (!fifo_isfull(&ser_handles[SER_SPI0]->rxfifo))
927 fifo_push(&ser_handles[SER_SPI0]->rxfifo, c);
931 ser_handles[SER_SPI0]->status |= SERRF_RXFIFOOVERRUN;
935 if (!fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
936 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
938 UARTDescs[SER_SPI0].sending = false;
948 * SPI1 interrupt handler
950 static DECLARE_ISR(spi1_irq_handler)
955 /* Read incoming byte. */
956 if (!fifo_isfull(&ser_handles[SER_SPI1]->rxfifo))
957 fifo_push(&ser_handles[SER_SPI1]->rxfifo, c);
961 ser_handles[SER_SPI1]->status |= SERRF_RXFIFOOVERRUN;
965 if (!fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
966 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
968 UARTDescs[SER_SPI1].sending = false;