4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \author Daniele Basile <asterix@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
45 #include <cfg/debug.h>
50 #include <drv/irq_cm3.h>
55 #include <drv/ser_p.h>
57 #include <struct/fifobuf.h>
60 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
63 * \name Overridable serial bus hooks
65 * These can be redefined in hw.h to implement
66 * special bus policies such as half-duplex, 485, etc.
70 * TXBEGIN TXCHAR TXEND TXOFF
71 * | __________|__________ | |
74 * ______ __ __ __ __ __ __ ________________
75 * \/ \/ \/ \/ \/ \/ \/
76 * ______/\__/\__/\__/\__/\__/\__/
83 #ifndef SER_UART0_BUS_TXINIT
85 * Default TXINIT macro - invoked in uart0_init()
87 * - Disable GPIO on USART0 tx/rx pins
89 #if CPU_ARM_AT91 && !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
90 #warning Check USART0 pins!
92 #define SER_UART0_BUS_TXINIT do { \
93 PIOA_PDR = BV(RXD0) | BV(TXD0); \
97 #ifndef SER_UART0_BUS_TXBEGIN
99 * Invoked before starting a transmission
101 #define SER_UART0_BUS_TXBEGIN
104 #ifndef SER_UART0_BUS_TXCHAR
106 * Invoked to send one character.
108 #define SER_UART0_BUS_TXCHAR(c) do { \
113 #ifndef SER_UART0_BUS_TXEND
115 * Invoked as soon as the txfifo becomes empty
117 #define SER_UART0_BUS_TXEND
120 /* End USART0 macros */
124 #ifndef SER_UART1_BUS_TXINIT
126 * Default TXINIT macro - invoked in uart1_init()
128 * - Disable GPIO on USART1 tx/rx pins
130 #if CPU_ARM_AT91 && !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
131 #warning Check USART1 pins!
133 #define SER_UART1_BUS_TXINIT do { \
134 PIOA_PDR = BV(RXD1) | BV(TXD1); \
138 #ifndef SER_UART1_BUS_TXBEGIN
140 * Invoked before starting a transmission
142 #define SER_UART1_BUS_TXBEGIN
145 #ifndef SER_UART1_BUS_TXCHAR
147 * Invoked to send one character.
149 #define SER_UART1_BUS_TXCHAR(c) do { \
154 #ifndef SER_UART1_BUS_TXEND
156 * Invoked as soon as the txfifo becomes empty
158 #define SER_UART1_BUS_TXEND
164 * \name Overridable SPI hooks
166 * These can be redefined in hw.h to implement
167 * special bus policies such as slave select pin handling, etc.
172 #ifndef SER_SPI0_BUS_TXINIT
174 * Default TXINIT macro - invoked in spi_init()
175 * The default is no action.
178 #define SER_SPI0_BUS_TXINIT do { \
179 /* Disable PIO on SPI pins */ \
180 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
181 /* PIO is peripheral A */ \
182 PIOA_ABCDSR1 &= ~(BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO)); \
183 PIOA_ABCDSR2 &= ~(BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO)); \
186 #define SER_SPI0_BUS_TXINIT do { \
187 /* Disable PIO on SPI pins */ \
188 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
193 #ifndef SER_SPI0_BUS_TXCLOSE
195 * Invoked after the last character has been transmitted.
196 * The default is no action.
198 #define SER_SPI0_BUS_TXCLOSE do { \
199 /* Enable PIO on SPI pins */ \
200 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
206 #ifndef SER_SPI1_BUS_TXINIT
208 * Default TXINIT macro - invoked in spi_init()
209 * The default is no action.
211 #define SER_SPI1_BUS_TXINIT do { \
212 /* Disable PIO on SPI pins */ \
213 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
214 /* SPI1 pins are on B peripheral function! */ \
215 PIOA_BSR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
219 #ifndef SER_SPI1_BUS_TXCLOSE
221 * Invoked after the last character has been transmitted.
222 * The default is no action.
224 #define SER_SPI1_BUS_TXCLOSE do { \
225 /* Enable PIO on SPI pins */ \
226 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
234 * \name Core dependent interrupt handling macros
236 * Atmel serial hardware is used on different CPU cores,
237 * i.e. SAM3 and SAM7. The user interface of the serial
238 * subsystem is identical but core interrupt controllers
245 INLINE void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler)
247 /* Set the vector. */
248 AIC_SVR(irq) = uart0_irq_dispatcher;
250 /* Initialize to level/edge sensitive with defined priority. */
252 if (irq == SPI0_ID || irq == SPI1_ID)
256 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_SRCTYPE_MASK) | AIC_SRCTYPE_INT_EDGE_TRIGGERED;
258 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_SRCTYPE_MASK) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE;
264 INLINE void sysirq_setPriority(sysirq_t irq, int prio)
266 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_PRIOR_MASK) | SERIRQ_PRIORITY;
269 /** Inform hw that we have served the IRQ */
270 #define SER_INT_ACK do { \
276 /** Inform hw that we have served the IRQ */
277 #define SER_INT_ACK do { /* nop */ } while (0)
280 #error No interrupt handling macros defined for current architecture
285 /* From the high-level serial driver */
286 extern struct Serial *ser_handles[SER_CNT];
288 /* TX and RX buffers */
289 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
290 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
292 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
293 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
295 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
296 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
298 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
299 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
303 * Internal hardware state structure
305 * The \a sending variable is true while the transmission
306 * interrupt is retriggering itself.
308 * For the USARTs the \a sending flag is useful for taking specific
309 * actions before sending a burst of data, at the start of a trasmission
310 * but not before every char sent.
312 * For the SPI, this flag is necessary because the SPI sends and receives
313 * bytes at the same time and the SPI IRQ is unique for send/receive.
314 * The only way to start transmission is to write data in SPDR (this
315 * is done by spi_starttx()). We do this *only* if a transfer is
316 * not already started.
320 struct SerialHardware hw;
321 volatile bool sending;
324 static ISR_PROTO(uart0_irq_dispatcher);
326 static ISR_PROTO(uart1_irq_dispatcher);
328 static ISR_PROTO(spi0_irq_handler);
330 static ISR_PROTO(spi1_irq_handler);
333 * Callbacks for USART0
335 static void uart0_init(
336 UNUSED_ARG(struct SerialHardware *, _hw),
337 UNUSED_ARG(struct Serial *, ser))
339 US0_IDR = 0xFFFFFFFF;
340 PMC_PCER = BV(US0_ID);
344 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
345 * - Enable both the receiver and the transmitter
346 * - Enable only the RX complete interrupt
348 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
349 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
350 US0_CR = BV(US_RXEN) | BV(US_TXEN);
351 US0_IER = BV(US_RXRDY);
353 SER_UART0_BUS_TXINIT;
355 sysirq_setPriority(INT_US0, SERIRQ_PRIORITY);
356 sysirq_setHandler(INT_US0, uart0_irq_dispatcher);
361 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
363 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
366 static void uart0_enabletxirq(struct SerialHardware *_hw)
368 struct ArmSerial *hw = (struct ArmSerial *)_hw;
371 * WARNING: racy code here! The tx interrupt sets hw->sending to false
372 * when it runs with an empty fifo. The order of statements in the
379 * - Enable the transmitter
380 * - Enable TX empty interrupt
382 SER_UART0_BUS_TXBEGIN;
383 US0_IER = BV(US_TXEMPTY);
387 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
389 /* Compute baud-rate period */
390 US0_BRGR = CPU_FREQ / (16 * rate);
391 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
394 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
396 US0_MR &= ~US_PAR_MASK;
397 /* Set UART parity */
400 case SER_PARITY_NONE:
406 case SER_PARITY_EVEN:
409 US0_MR |= US_PAR_EVEN;
415 US0_MR |= US_PAR_ODD;
426 * Callbacks for USART1
428 static void uart1_init(
429 UNUSED_ARG(struct SerialHardware *, _hw),
430 UNUSED_ARG(struct Serial *, ser))
432 US1_IDR = 0xFFFFFFFF;
433 PMC_PCER = BV(US1_ID);
437 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
438 * - Enable both the receiver and the transmitter
439 * - Enable only the RX complete interrupt
441 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
442 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
443 US1_CR = BV(US_RXEN) | BV(US_TXEN);
444 US1_IER = BV(US_RXRDY);
446 SER_UART1_BUS_TXINIT;
448 sysirq_setPriority(INT_US1, SERIRQ_PRIORITY);
449 sysirq_setHandler(INT_US1, uart1_irq_dispatcher);
454 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
456 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
459 static void uart1_enabletxirq(struct SerialHardware *_hw)
461 struct ArmSerial *hw = (struct ArmSerial *)_hw;
464 * WARNING: racy code here! The tx interrupt sets hw->sending to false
465 * when it runs with an empty fifo. The order of statements in the
472 * - Enable the transmitter
473 * - Enable TX empty interrupt
475 SER_UART1_BUS_TXBEGIN;
476 US1_IER = BV(US_TXEMPTY);
480 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
482 /* Compute baud-rate period */
483 US1_BRGR = CPU_FREQ / (16 * rate);
484 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
487 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
489 US1_MR &= ~US_PAR_MASK;
490 /* Set UART parity */
493 case SER_PARITY_NONE:
499 case SER_PARITY_EVEN:
502 US1_MR |= US_PAR_EVEN;
508 US1_MR |= US_PAR_ODD;
516 #endif /* USART_PORTS > 1 */
519 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
524 SPI0_CR = BV(SPI_SWRST);
527 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
528 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
530 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
534 * At reset clock division factor is set to 0, that is
535 * *forbidden*. Set SPI clock to minimum to keep it valid.
536 * Set all possible chip select registers in case user manually
537 * change CPS field in SPI_MR.
539 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
540 SPI0_CSR1 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
541 SPI0_CSR2 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
542 SPI0_CSR3 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
544 /* Disable all irqs */
545 SPI0_IDR = 0xFFFFFFFF;
547 //sysirq_setPriority(INT_SPI0, SERIRQ_PRIORITY);
548 sysirq_setHandler(INT_SPI0, spi0_irq_handler);
549 PMC_PCER = BV(SPI0_ID);
552 SPI0_CR = BV(SPI_SPIEN);
557 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
560 SPI0_CR = BV(SPI_SPIDIS);
562 /* Disable all irqs */
563 SPI0_IDR = 0xFFFFFFFF;
565 SER_SPI0_BUS_TXCLOSE;
568 static void spi0_starttx(struct SerialHardware *_hw)
570 struct ArmSerial *hw = (struct ArmSerial *)_hw;
573 IRQ_SAVE_DISABLE(flags);
575 /* Send data only if the SPI is not already transmitting */
576 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
579 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
580 /* Enable interrupt on tx buffer empty */
581 SPI0_IER = BV(SPI_TXEMPTY);
587 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
589 SPI0_CSR0 &= ~SPI_SCBR;
591 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
592 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
597 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
602 SPI1_CR = BV(SPI_SWRST);
605 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
606 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
608 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
612 * At reset clock division factor is set to 0, that is
613 * *forbidden*. Set SPI clock to minimum to keep it valid.
614 * Set all possible chip select registers in case user manually
615 * change chip select.
617 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
618 SPI1_CSR1 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
619 SPI1_CSR2 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
620 SPI1_CSR3 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
622 /* Disable all SPI irqs */
623 SPI1_IDR = 0xFFFFFFFF;
625 sysirq_setPriority(INT_SPI1, SERIRQ_PRIORITY);
626 sysirq_setHandler(INT_SPI1, spi1_irq_dispatcher);
627 PMC_PCER = BV(SPI1_ID);
630 SPI1_CR = BV(SPI_SPIEN);
635 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
638 SPI1_CR = BV(SPI_SPIDIS);
640 /* Disable all irqs */
641 SPI1_IDR = 0xFFFFFFFF;
643 SER_SPI1_BUS_TXCLOSE;
646 static void spi1_starttx(struct SerialHardware *_hw)
648 struct ArmSerial *hw = (struct ArmSerial *)_hw;
651 IRQ_SAVE_DISABLE(flags);
653 /* Send data only if the SPI is not already transmitting */
654 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
657 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
658 /* Enable interrupt on tx buffer empty */
659 SPI1_IER = BV(SPI_TXEMPTY);
665 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
667 SPI1_CSR0 &= ~SPI_SCBR;
669 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
670 SPI1_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
674 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
680 static bool tx_sending(struct SerialHardware* _hw)
682 struct ArmSerial *hw = (struct ArmSerial *)_hw;
686 // FIXME: move into compiler.h? Ditch?
688 #define C99INIT(name,val) .name = val
689 #elif defined(__GNUC__)
690 #define C99INIT(name,val) name: val
692 #warning No designated initializers, double check your code
693 #define C99INIT(name,val) (val)
697 * High-level interface data structures
699 static const struct SerialHardwareVT UART0_VT =
701 C99INIT(init, uart0_init),
702 C99INIT(cleanup, uart0_cleanup),
703 C99INIT(setBaudrate, uart0_setbaudrate),
704 C99INIT(setParity, uart0_setparity),
705 C99INIT(txStart, uart0_enabletxirq),
706 C99INIT(txSending, tx_sending),
711 static const struct SerialHardwareVT UART1_VT =
713 C99INIT(init, uart1_init),
714 C99INIT(cleanup, uart1_cleanup),
715 C99INIT(setBaudrate, uart1_setbaudrate),
716 C99INIT(setParity, uart1_setparity),
717 C99INIT(txStart, uart1_enabletxirq),
718 C99INIT(txSending, tx_sending),
721 #endif /* USART_PORTS > 1 */
723 static const struct SerialHardwareVT SPI0_VT =
725 C99INIT(init, spi0_init),
726 C99INIT(cleanup, spi0_cleanup),
727 C99INIT(setBaudrate, spi0_setbaudrate),
728 C99INIT(setParity, spi_setparity),
729 C99INIT(txStart, spi0_starttx),
730 C99INIT(txSending, tx_sending),
733 static const struct SerialHardwareVT SPI1_VT =
735 C99INIT(init, spi1_init),
736 C99INIT(cleanup, spi1_cleanup),
737 C99INIT(setBaudrate, spi1_setbaudrate),
738 C99INIT(setParity, spi_setparity),
739 C99INIT(txStart, spi1_starttx),
740 C99INIT(txSending, tx_sending),
744 static struct ArmSerial UARTDescs[SER_CNT] =
748 C99INIT(table, &UART0_VT),
749 C99INIT(txbuffer, uart0_txbuffer),
750 C99INIT(rxbuffer, uart0_rxbuffer),
751 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
752 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
754 C99INIT(sending, false),
759 C99INIT(table, &UART1_VT),
760 C99INIT(txbuffer, uart1_txbuffer),
761 C99INIT(rxbuffer, uart1_rxbuffer),
762 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
763 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
765 C99INIT(sending, false),
771 C99INIT(table, &SPI0_VT),
772 C99INIT(txbuffer, spi0_txbuffer),
773 C99INIT(rxbuffer, spi0_rxbuffer),
774 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
775 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
777 C99INIT(sending, false),
782 C99INIT(table, &SPI1_VT),
783 C99INIT(txbuffer, spi1_txbuffer),
784 C99INIT(rxbuffer, spi1_rxbuffer),
785 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
786 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
788 C99INIT(sending, false),
794 struct SerialHardware *ser_hw_getdesc(int unit)
796 ASSERT(unit < SER_CNT);
797 return &UARTDescs[unit].hw;
801 * Serial 0 TX interrupt handler
803 INLINE void uart0_irq_tx(void)
807 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
809 if (fifo_isempty(txfifo))
812 * - Disable the TX empty interrupts
814 US0_IDR = BV(US_TXEMPTY);
816 UARTDescs[SER_UART0].sending = false;
820 char c = fifo_pop(txfifo);
821 SER_UART0_BUS_TXCHAR(c);
828 * Serial 0 RX complete interrupt handler.
830 INLINE void uart0_irq_rx(void)
834 /* Should be read before US_CRS */
835 ser_handles[SER_UART0]->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
836 US0_CR = BV(US_RSTSTA);
839 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
841 if (fifo_isfull(rxfifo))
842 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
844 fifo_push(rxfifo, c);
850 * Serial IRQ dispatcher for USART0.
852 static DECLARE_ISR(uart0_irq_dispatcher)
854 if (US0_CSR & BV(US_RXRDY))
857 if (US0_CSR & BV(US_TXEMPTY))
866 * Serial 1 TX interrupt handler
868 INLINE void uart1_irq_tx(void)
872 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
874 if (fifo_isempty(txfifo))
877 * - Disable the TX empty interrupts
879 US1_IDR = BV(US_TXEMPTY);
881 UARTDescs[SER_UART1].sending = false;
885 char c = fifo_pop(txfifo);
886 SER_UART1_BUS_TXCHAR(c);
893 * Serial 1 RX complete interrupt handler.
895 INLINE void uart1_irq_rx(void)
899 /* Should be read before US_CRS */
900 ser_handles[SER_UART1]->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
901 US1_CR = BV(US_RSTSTA);
904 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
906 if (fifo_isfull(rxfifo))
907 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
909 fifo_push(rxfifo, c);
915 * Serial IRQ dispatcher for USART1.
917 static DECLARE_ISR(uart1_irq_dispatcher)
919 if (US1_CSR & BV(US_RXRDY))
922 if (US1_CSR & BV(US_TXEMPTY))
928 #endif /* USART_PORTS > 1 */
931 * SPI0 interrupt handler
933 static DECLARE_ISR(spi0_irq_handler)
938 /* Read incoming byte. */
939 if (!fifo_isfull(&ser_handles[SER_SPI0]->rxfifo))
940 fifo_push(&ser_handles[SER_SPI0]->rxfifo, c);
944 ser_handles[SER_SPI0]->status |= SERRF_RXFIFOOVERRUN;
948 if (!fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
949 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
952 UARTDescs[SER_SPI0].sending = false;
953 /* Disable interrupt on tx buffer empty */
954 SPI0_IDR = BV(SPI_TXEMPTY);
965 * SPI1 interrupt handler
967 static DECLARE_ISR(spi1_irq_handler)
972 /* Read incoming byte. */
973 if (!fifo_isfull(&ser_handles[SER_SPI1]->rxfifo))
974 fifo_push(&ser_handles[SER_SPI1]->rxfifo, c);
978 ser_handles[SER_SPI1]->status |= SERRF_RXFIFOOVERRUN;
982 if (!fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
983 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
986 UARTDescs[SER_SPI1].sending = false;
987 /* Disable interrupt on tx buffer empty */
988 SPI1_IDR = BV(SPI_TXEMPTY);