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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 Synchronous Serial Interface (SSI) driver.
35 * \author Andrea Righi <arighi@develer.com>
41 #include <cfg/compiler.h>
42 #include <cfg/debug.h>
44 #include <string.h> /* memset() */
46 /* SSI clocking informations (CPSDVSR + SCR) */
54 * Evaluate the SSI clock prescale (SSICPSR) and SSI serial clock rate (SCR).
56 INLINE struct SSIClock
57 lm3s_ssiPrescale(unsigned int bitrate)
61 for (ret.cpsdvsr = 2, ret.scr = CPU_FREQ / bitrate / ret.cpsdvsr - 1;
62 ret.scr > 255; ret.cpsdvsr += 2);
63 ASSERT(ret.cpsdvsr < 255);
69 * Initialize the SSI interface.
71 * Return 0 in case of success, a negative value otherwise.
73 int lm3s_ssiOpen(uint32_t addr, uint32_t frame, int mode,
74 int bitrate, uint32_t data_width)
76 struct SSIClock ssi_clock;
78 ASSERT(addr == SSI0_BASE || addr == SSI1_BASE);
79 /* Configure the SSI operating mode */
82 /* SSI Slave Mode Output Disable */
83 case SSI_MODE_SLAVE_OD:
84 HWREG(addr + SSI_O_CR1) = SSI_CR1_SOD;
88 HWREG(addr + SSI_O_CR1) = SSI_CR1_MS;
92 HWREG(addr + SSI_O_CR1) = 0;
98 /* Configure the peripheral clock and frame format */
99 ssi_clock = lm3s_ssiPrescale(bitrate);
100 HWREG(addr + SSI_O_CPSR) = ssi_clock.cpsdvsr;
101 HWREG(addr + SSI_O_CR0) =
102 (ssi_clock.scr << 8) |
104 (frame & SSI_CR0_FRF_M) |
106 /* Enable the SSI interface */
107 HWREG(addr + SSI_O_CR1) |= SSI_CR1_SSE;
113 * Write data to the SSI bus.
115 * Return the number of bytes written to the bus.
117 static size_t lm3s_ssiWrite(struct KFile *fd, const void *buf, size_t size)
119 LM3SSSI *fds = LM3SSSI_CAST(fd);
120 const char *p = (const char *)buf;
127 if (fds->flags & LM3S_SSI_NONBLOCK)
129 if (!lm3s_ssiWriteFrameNonBlocking(fds->addr,
134 lm3s_ssiWriteFrame(fds->addr, frame);
141 * Read data from the SSI bus.
143 * Return the number of bytes read from the bus.
145 static size_t lm3s_ssiRead(struct KFile *fd, void *buf, size_t size)
147 LM3SSSI *fds = LM3SSSI_CAST(fd);
149 uint8_t *p = (uint8_t *)buf;
155 if (fds->flags & LM3S_SSI_NONBLOCK)
157 if (!lm3s_ssiReadFrameNonBlocking(fds->addr, &frame))
161 lm3s_ssiReadFrame(fds->addr, &frame);
162 *p++ = (uint8_t)frame;
169 /* Wait for data in the TX FIFO being actually transmitted */
170 static int lm3s_ssiFlush(struct KFile *fd)
172 LM3SSSI *fds = LM3SSSI_CAST(fd);
174 while (!lm3s_ssiTxDone(fds->addr))
179 /* Disable the SSI interface */
180 static int lm3s_ssiClose(struct KFile *fd)
182 LM3SSSI *fds = LM3SSSI_CAST(fd);
185 HWREG(fds->addr + SSI_O_CR1) &= ~SSI_CR1_SSE;
190 * Initialize a LM3S SSI driver.
192 void lm3s_ssiInit(struct LM3SSSI *fds, uint32_t addr, uint32_t frame, int mode,
193 int bitrate, uint32_t data_width)
195 memset(fds, 0, sizeof(*fds));
196 DB(fds->fd._type = KFT_LM3SSSI);
198 /* TODO: only 8-bit frame size is supported */
199 ASSERT(data_width == 8);
201 fds->fd.write = lm3s_ssiWrite;
202 fds->fd.read = lm3s_ssiRead;
203 fds->fd.close = lm3s_ssiClose;
204 fds->fd.flush = lm3s_ssiFlush;
207 lm3s_ssiOpen(addr, frame, mode, bitrate, data_width);