4 * This file is part of BeRTOS.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 startup interrupt vector table
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/compiler.h>
39 #include <cpu/attr.h> /* PAUSE, UNREACHABLE */
41 extern size_t __stack_end;
42 extern void __init(void);
44 static void NORETURN NAKED default_isr(void)
50 static void (* const irq_vectors[])(void) __attribute__ ((section(".vectors"))) =
52 (void (*)(void))&__stack_end, /* Initial stack pointer */
53 __init, /* The reset handler */
54 default_isr, /* The NMI handler */
55 default_isr, /* The hard fault handler */
56 default_isr, /* The MPU fault handler */
57 default_isr, /* The bus fault handler */
58 default_isr, /* The usage fault handler */
63 default_isr, /* SVCall handler */
64 default_isr, /* Debug monitor handler */
66 default_isr, /* The PendSV handler */
67 default_isr, /* The SysTick handler */
68 default_isr, /* GPIO Port A */
69 default_isr, /* GPIO Port B */
70 default_isr, /* GPIO Port C */
71 default_isr, /* GPIO Port D */
72 default_isr, /* GPIO Port E */
73 default_isr, /* UART0 Rx and Tx */
74 default_isr, /* UART1 Rx and Tx */
75 default_isr, /* SSI0 Rx and Tx */
76 default_isr, /* I2C0 Master and Slave */
77 default_isr, /* PWM Fault */
78 default_isr, /* PWM Generator 0 */
79 default_isr, /* PWM Generator 1 */
80 default_isr, /* PWM Generator 2 */
81 default_isr, /* Quadrature Encoder 0 */
82 default_isr, /* ADC Sequence 0 */
83 default_isr, /* ADC Sequence 1 */
84 default_isr, /* ADC Sequence 2 */
85 default_isr, /* ADC Sequence 3 */
86 default_isr, /* Watchdog timer */
87 default_isr, /* Timer 0 subtimer A */
88 default_isr, /* Timer 0 subtimer B */
89 default_isr, /* Timer 1 subtimer A */
90 default_isr, /* Timer 1 subtimer B */
91 default_isr, /* Timer 2 subtimer A */
92 default_isr, /* Timer 2 subtimer B */
93 default_isr, /* Analog Comparator 0 */
94 default_isr, /* Analog Comparator 1 */
95 default_isr, /* Analog Comparator 2 */
96 default_isr, /* System Control (PLL, OSC, BO) */
97 default_isr, /* FLASH Control */
98 default_isr, /* GPIO Port F */
99 default_isr, /* GPIO Port G */
100 default_isr, /* GPIO Port H */
101 default_isr, /* UART2 Rx and Tx */
102 default_isr, /* SSI1 Rx and Tx */
103 default_isr, /* Timer 3 subtimer A */
104 default_isr, /* Timer 3 subtimer B */
105 default_isr, /* I2C1 Master and Slave */
106 default_isr, /* Quadrature Encoder 1 */
107 default_isr, /* CAN0 */
108 default_isr, /* CAN1 */
109 default_isr, /* CAN2 */
110 default_isr, /* Ethernet */
111 default_isr /* Hibernate */