4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 registers definition.
39 #include <cfg/compiler.h>
42 * Watchdog Timer registers (WATCHDOG0)
45 #define WATCHDOG0_LOAD_R (*((reg32_t *)0x40000000))
46 #define WATCHDOG0_VALUE_R (*((reg32_t *)0x40000004))
47 #define WATCHDOG0_CTL_R (*((reg32_t *)0x40000008))
48 #define WATCHDOG0_ICR_R (*((reg32_t *)0x4000000C))
49 #define WATCHDOG0_RIS_R (*((reg32_t *)0x40000010))
50 #define WATCHDOG0_MIS_R (*((reg32_t *)0x40000014))
51 #define WATCHDOG0_TEST_R (*((reg32_t *)0x40000418))
52 #define WATCHDOG0_LOCK_R (*((reg32_t *)0x40000C00))
56 * GPIO registers (PORTA)
59 #define GPIO_PORTA_DATA_BITS_R ((reg32_t *)0x40004000)
60 #define GPIO_PORTA_DATA_R (*((reg32_t *)0x400043FC))
61 #define GPIO_PORTA_DIR_R (*((reg32_t *)0x40004400))
62 #define GPIO_PORTA_IS_R (*((reg32_t *)0x40004404))
63 #define GPIO_PORTA_IBE_R (*((reg32_t *)0x40004408))
64 #define GPIO_PORTA_IEV_R (*((reg32_t *)0x4000440C))
65 #define GPIO_PORTA_IM_R (*((reg32_t *)0x40004410))
66 #define GPIO_PORTA_RIS_R (*((reg32_t *)0x40004414))
67 #define GPIO_PORTA_MIS_R (*((reg32_t *)0x40004418))
68 #define GPIO_PORTA_ICR_R (*((reg32_t *)0x4000441C))
69 #define GPIO_PORTA_AFSEL_R (*((reg32_t *)0x40004420))
70 #define GPIO_PORTA_DR2R_R (*((reg32_t *)0x40004500))
71 #define GPIO_PORTA_DR4R_R (*((reg32_t *)0x40004504))
72 #define GPIO_PORTA_DR8R_R (*((reg32_t *)0x40004508))
73 #define GPIO_PORTA_ODR_R (*((reg32_t *)0x4000450C))
74 #define GPIO_PORTA_PUR_R (*((reg32_t *)0x40004510))
75 #define GPIO_PORTA_PDR_R (*((reg32_t *)0x40004514))
76 #define GPIO_PORTA_SLR_R (*((reg32_t *)0x40004518))
77 #define GPIO_PORTA_DEN_R (*((reg32_t *)0x4000451C))
78 #define GPIO_PORTA_LOCK_R (*((reg32_t *)0x40004520))
79 #define GPIO_PORTA_CR_R (*((reg32_t *)0x40004524))
83 * GPIO registers (PORTB)
86 #define GPIO_PORTB_DATA_BITS_R ((reg32_t *)0x40005000)
87 #define GPIO_PORTB_DATA_R (*((reg32_t *)0x400053FC))
88 #define GPIO_PORTB_DIR_R (*((reg32_t *)0x40005400))
89 #define GPIO_PORTB_IS_R (*((reg32_t *)0x40005404))
90 #define GPIO_PORTB_IBE_R (*((reg32_t *)0x40005408))
91 #define GPIO_PORTB_IEV_R (*((reg32_t *)0x4000540C))
92 #define GPIO_PORTB_IM_R (*((reg32_t *)0x40005410))
93 #define GPIO_PORTB_RIS_R (*((reg32_t *)0x40005414))
94 #define GPIO_PORTB_MIS_R (*((reg32_t *)0x40005418))
95 #define GPIO_PORTB_ICR_R (*((reg32_t *)0x4000541C))
96 #define GPIO_PORTB_AFSEL_R (*((reg32_t *)0x40005420))
97 #define GPIO_PORTB_DR2R_R (*((reg32_t *)0x40005500))
98 #define GPIO_PORTB_DR4R_R (*((reg32_t *)0x40005504))
99 #define GPIO_PORTB_DR8R_R (*((reg32_t *)0x40005508))
100 #define GPIO_PORTB_ODR_R (*((reg32_t *)0x4000550C))
101 #define GPIO_PORTB_PUR_R (*((reg32_t *)0x40005510))
102 #define GPIO_PORTB_PDR_R (*((reg32_t *)0x40005514))
103 #define GPIO_PORTB_SLR_R (*((reg32_t *)0x40005518))
104 #define GPIO_PORTB_DEN_R (*((reg32_t *)0x4000551C))
105 #define GPIO_PORTB_LOCK_R (*((reg32_t *)0x40005520))
106 #define GPIO_PORTB_CR_R (*((reg32_t *)0x40005524))
110 * GPIO registers (PORTC)
113 #define GPIO_PORTC_DATA_BITS_R ((reg32_t *)0x40006000)
114 #define GPIO_PORTC_DATA_R (*((reg32_t *)0x400063FC))
115 #define GPIO_PORTC_DIR_R (*((reg32_t *)0x40006400))
116 #define GPIO_PORTC_IS_R (*((reg32_t *)0x40006404))
117 #define GPIO_PORTC_IBE_R (*((reg32_t *)0x40006408))
118 #define GPIO_PORTC_IEV_R (*((reg32_t *)0x4000640C))
119 #define GPIO_PORTC_IM_R (*((reg32_t *)0x40006410))
120 #define GPIO_PORTC_RIS_R (*((reg32_t *)0x40006414))
121 #define GPIO_PORTC_MIS_R (*((reg32_t *)0x40006418))
122 #define GPIO_PORTC_ICR_R (*((reg32_t *)0x4000641C))
123 #define GPIO_PORTC_AFSEL_R (*((reg32_t *)0x40006420))
124 #define GPIO_PORTC_DR2R_R (*((reg32_t *)0x40006500))
125 #define GPIO_PORTC_DR4R_R (*((reg32_t *)0x40006504))
126 #define GPIO_PORTC_DR8R_R (*((reg32_t *)0x40006508))
127 #define GPIO_PORTC_ODR_R (*((reg32_t *)0x4000650C))
128 #define GPIO_PORTC_PUR_R (*((reg32_t *)0x40006510))
129 #define GPIO_PORTC_PDR_R (*((reg32_t *)0x40006514))
130 #define GPIO_PORTC_SLR_R (*((reg32_t *)0x40006518))
131 #define GPIO_PORTC_DEN_R (*((reg32_t *)0x4000651C))
132 #define GPIO_PORTC_LOCK_R (*((reg32_t *)0x40006520))
133 #define GPIO_PORTC_CR_R (*((reg32_t *)0x40006524))
137 * GPIO registers (PORTD)
140 #define GPIO_PORTD_DATA_BITS_R ((reg32_t *)0x40007000)
141 #define GPIO_PORTD_DATA_R (*((reg32_t *)0x400073FC))
142 #define GPIO_PORTD_DIR_R (*((reg32_t *)0x40007400))
143 #define GPIO_PORTD_IS_R (*((reg32_t *)0x40007404))
144 #define GPIO_PORTD_IBE_R (*((reg32_t *)0x40007408))
145 #define GPIO_PORTD_IEV_R (*((reg32_t *)0x4000740C))
146 #define GPIO_PORTD_IM_R (*((reg32_t *)0x40007410))
147 #define GPIO_PORTD_RIS_R (*((reg32_t *)0x40007414))
148 #define GPIO_PORTD_MIS_R (*((reg32_t *)0x40007418))
149 #define GPIO_PORTD_ICR_R (*((reg32_t *)0x4000741C))
150 #define GPIO_PORTD_AFSEL_R (*((reg32_t *)0x40007420))
151 #define GPIO_PORTD_DR2R_R (*((reg32_t *)0x40007500))
152 #define GPIO_PORTD_DR4R_R (*((reg32_t *)0x40007504))
153 #define GPIO_PORTD_DR8R_R (*((reg32_t *)0x40007508))
154 #define GPIO_PORTD_ODR_R (*((reg32_t *)0x4000750C))
155 #define GPIO_PORTD_PUR_R (*((reg32_t *)0x40007510))
156 #define GPIO_PORTD_PDR_R (*((reg32_t *)0x40007514))
157 #define GPIO_PORTD_SLR_R (*((reg32_t *)0x40007518))
158 #define GPIO_PORTD_DEN_R (*((reg32_t *)0x4000751C))
159 #define GPIO_PORTD_LOCK_R (*((reg32_t *)0x40007520))
160 #define GPIO_PORTD_CR_R (*((reg32_t *)0x40007524))
164 * SSI registers (SSI0)
167 #define SSI0_CR0_R (*((reg32_t *)0x40008000))
168 #define SSI0_CR1_R (*((reg32_t *)0x40008004))
169 #define SSI0_DR_R (*((reg32_t *)0x40008008))
170 #define SSI0_SR_R (*((reg32_t *)0x4000800C))
171 #define SSI0_CPSR_R (*((reg32_t *)0x40008010))
172 #define SSI0_IM_R (*((reg32_t *)0x40008014))
173 #define SSI0_RIS_R (*((reg32_t *)0x40008018))
174 #define SSI0_MIS_R (*((reg32_t *)0x4000801C))
175 #define SSI0_ICR_R (*((reg32_t *)0x40008020))
179 * SSI registers (SSI1)
182 #define SSI1_CR0_R (*((reg32_t *)0x40009000))
183 #define SSI1_CR1_R (*((reg32_t *)0x40009004))
184 #define SSI1_DR_R (*((reg32_t *)0x40009008))
185 #define SSI1_SR_R (*((reg32_t *)0x4000900C))
186 #define SSI1_CPSR_R (*((reg32_t *)0x40009010))
187 #define SSI1_IM_R (*((reg32_t *)0x40009014))
188 #define SSI1_RIS_R (*((reg32_t *)0x40009018))
189 #define SSI1_MIS_R (*((reg32_t *)0x4000901C))
190 #define SSI1_ICR_R (*((reg32_t *)0x40009020))
194 * UART registers (UART0)
197 #define UART0_DR_R (*((reg32_t *)0x4000C000))
198 #define UART0_RSR_R (*((reg32_t *)0x4000C004))
199 #define UART0_ECR_R (*((reg32_t *)0x4000C004))
200 #define UART0_FR_R (*((reg32_t *)0x4000C018))
201 #define UART0_ILPR_R (*((reg32_t *)0x4000C020))
202 #define UART0_IBRD_R (*((reg32_t *)0x4000C024))
203 #define UART0_FBRD_R (*((reg32_t *)0x4000C028))
204 #define UART0_LCRH_R (*((reg32_t *)0x4000C02C))
205 #define UART0_CTL_R (*((reg32_t *)0x4000C030))
206 #define UART0_IFLS_R (*((reg32_t *)0x4000C034))
207 #define UART0_IM_R (*((reg32_t *)0x4000C038))
208 #define UART0_RIS_R (*((reg32_t *)0x4000C03C))
209 #define UART0_MIS_R (*((reg32_t *)0x4000C040))
210 #define UART0_ICR_R (*((reg32_t *)0x4000C044))
214 * UART registers (UART1)
217 #define UART1_DR_R (*((reg32_t *)0x4000D000))
218 #define UART1_RSR_R (*((reg32_t *)0x4000D004))
219 #define UART1_ECR_R (*((reg32_t *)0x4000D004))
220 #define UART1_FR_R (*((reg32_t *)0x4000D018))
221 #define UART1_ILPR_R (*((reg32_t *)0x4000D020))
222 #define UART1_IBRD_R (*((reg32_t *)0x4000D024))
223 #define UART1_FBRD_R (*((reg32_t *)0x4000D028))
224 #define UART1_LCRH_R (*((reg32_t *)0x4000D02C))
225 #define UART1_CTL_R (*((reg32_t *)0x4000D030))
226 #define UART1_IFLS_R (*((reg32_t *)0x4000D034))
227 #define UART1_IM_R (*((reg32_t *)0x4000D038))
228 #define UART1_RIS_R (*((reg32_t *)0x4000D03C))
229 #define UART1_MIS_R (*((reg32_t *)0x4000D040))
230 #define UART1_ICR_R (*((reg32_t *)0x4000D044))
234 * UART registers (UART2)
237 #define UART2_DR_R (*((reg32_t *)0x4000E000))
238 #define UART2_RSR_R (*((reg32_t *)0x4000E004))
239 #define UART2_ECR_R (*((reg32_t *)0x4000E004))
240 #define UART2_FR_R (*((reg32_t *)0x4000E018))
241 #define UART2_ILPR_R (*((reg32_t *)0x4000E020))
242 #define UART2_IBRD_R (*((reg32_t *)0x4000E024))
243 #define UART2_FBRD_R (*((reg32_t *)0x4000E028))
244 #define UART2_LCRH_R (*((reg32_t *)0x4000E02C))
245 #define UART2_CTL_R (*((reg32_t *)0x4000E030))
246 #define UART2_IFLS_R (*((reg32_t *)0x4000E034))
247 #define UART2_IM_R (*((reg32_t *)0x4000E038))
248 #define UART2_RIS_R (*((reg32_t *)0x4000E03C))
249 #define UART2_MIS_R (*((reg32_t *)0x4000E040))
250 #define UART2_ICR_R (*((reg32_t *)0x4000E044))
254 * I2C registers (I2C0 MASTER)
257 #define I2C0_MASTER_MSA_R (*((reg32_t *)0x40020000))
258 #define I2C0_MASTER_SOAR_R (*((reg32_t *)0x40020000))
259 #define I2C0_MASTER_SCSR_R (*((reg32_t *)0x40020004))
260 #define I2C0_MASTER_MCS_R (*((reg32_t *)0x40020004))
261 #define I2C0_MASTER_SDR_R (*((reg32_t *)0x40020008))
262 #define I2C0_MASTER_MDR_R (*((reg32_t *)0x40020008))
263 #define I2C0_MASTER_MTPR_R (*((reg32_t *)0x4002000C))
264 #define I2C0_MASTER_SIMR_R (*((reg32_t *)0x4002000C))
265 #define I2C0_MASTER_SRIS_R (*((reg32_t *)0x40020010))
266 #define I2C0_MASTER_MIMR_R (*((reg32_t *)0x40020010))
267 #define I2C0_MASTER_MRIS_R (*((reg32_t *)0x40020014))
268 #define I2C0_MASTER_SMIS_R (*((reg32_t *)0x40020014))
269 #define I2C0_MASTER_SICR_R (*((reg32_t *)0x40020018))
270 #define I2C0_MASTER_MMIS_R (*((reg32_t *)0x40020018))
271 #define I2C0_MASTER_MICR_R (*((reg32_t *)0x4002001C))
272 #define I2C0_MASTER_MCR_R (*((reg32_t *)0x40020020))
276 * I2C registers (I2C0 SLAVE)
279 #define I2C0_SLAVE_MSA_R (*((reg32_t *)0x40020800))
280 #define I2C0_SLAVE_SOAR_R (*((reg32_t *)0x40020800))
281 #define I2C0_SLAVE_SCSR_R (*((reg32_t *)0x40020804))
282 #define I2C0_SLAVE_MCS_R (*((reg32_t *)0x40020804))
283 #define I2C0_SLAVE_SDR_R (*((reg32_t *)0x40020808))
284 #define I2C0_SLAVE_MDR_R (*((reg32_t *)0x40020808))
285 #define I2C0_SLAVE_MTPR_R (*((reg32_t *)0x4002080C))
286 #define I2C0_SLAVE_SIMR_R (*((reg32_t *)0x4002080C))
287 #define I2C0_SLAVE_SRIS_R (*((reg32_t *)0x40020810))
288 #define I2C0_SLAVE_MIMR_R (*((reg32_t *)0x40020810))
289 #define I2C0_SLAVE_MRIS_R (*((reg32_t *)0x40020814))
290 #define I2C0_SLAVE_SMIS_R (*((reg32_t *)0x40020814))
291 #define I2C0_SLAVE_SICR_R (*((reg32_t *)0x40020818))
292 #define I2C0_SLAVE_MMIS_R (*((reg32_t *)0x40020818))
293 #define I2C0_SLAVE_MICR_R (*((reg32_t *)0x4002081C))
294 #define I2C0_SLAVE_MCR_R (*((reg32_t *)0x40020820))
298 * I2C registers (I2C1 MASTER)
301 #define I2C1_MASTER_MSA_R (*((reg32_t *)0x40021000))
302 #define I2C1_MASTER_SOAR_R (*((reg32_t *)0x40021000))
303 #define I2C1_MASTER_SCSR_R (*((reg32_t *)0x40021004))
304 #define I2C1_MASTER_MCS_R (*((reg32_t *)0x40021004))
305 #define I2C1_MASTER_SDR_R (*((reg32_t *)0x40021008))
306 #define I2C1_MASTER_MDR_R (*((reg32_t *)0x40021008))
307 #define I2C1_MASTER_MTPR_R (*((reg32_t *)0x4002100C))
308 #define I2C1_MASTER_SIMR_R (*((reg32_t *)0x4002100C))
309 #define I2C1_MASTER_SRIS_R (*((reg32_t *)0x40021010))
310 #define I2C1_MASTER_MIMR_R (*((reg32_t *)0x40021010))
311 #define I2C1_MASTER_MRIS_R (*((reg32_t *)0x40021014))
312 #define I2C1_MASTER_SMIS_R (*((reg32_t *)0x40021014))
313 #define I2C1_MASTER_SICR_R (*((reg32_t *)0x40021018))
314 #define I2C1_MASTER_MMIS_R (*((reg32_t *)0x40021018))
315 #define I2C1_MASTER_MICR_R (*((reg32_t *)0x4002101C))
316 #define I2C1_MASTER_MCR_R (*((reg32_t *)0x40021020))
320 * I2C registers (I2C1 SLAVE)
323 #define I2C1_SLAVE_MSA_R (*((reg32_t *)0x40021800))
324 #define I2C1_SLAVE_SOAR_R (*((reg32_t *)0x40021800))
325 #define I2C1_SLAVE_SCSR_R (*((reg32_t *)0x40021804))
326 #define I2C1_SLAVE_MCS_R (*((reg32_t *)0x40021804))
327 #define I2C1_SLAVE_SDR_R (*((reg32_t *)0x40021808))
328 #define I2C1_SLAVE_MDR_R (*((reg32_t *)0x40021808))
329 #define I2C1_SLAVE_MTPR_R (*((reg32_t *)0x4002180C))
330 #define I2C1_SLAVE_SIMR_R (*((reg32_t *)0x4002180C))
331 #define I2C1_SLAVE_SRIS_R (*((reg32_t *)0x40021810))
332 #define I2C1_SLAVE_MIMR_R (*((reg32_t *)0x40021810))
333 #define I2C1_SLAVE_MRIS_R (*((reg32_t *)0x40021814))
334 #define I2C1_SLAVE_SMIS_R (*((reg32_t *)0x40021814))
335 #define I2C1_SLAVE_SICR_R (*((reg32_t *)0x40021818))
336 #define I2C1_SLAVE_MMIS_R (*((reg32_t *)0x40021818))
337 #define I2C1_SLAVE_MICR_R (*((reg32_t *)0x4002181C))
338 #define I2C1_SLAVE_MCR_R (*((reg32_t *)0x40021820))
342 * GPIO registers (PORTE)
345 #define GPIO_PORTE_DATA_BITS_R ((reg32_t *)0x40024000)
346 #define GPIO_PORTE_DATA_R (*((reg32_t *)0x400243FC))
347 #define GPIO_PORTE_DIR_R (*((reg32_t *)0x40024400))
348 #define GPIO_PORTE_IS_R (*((reg32_t *)0x40024404))
349 #define GPIO_PORTE_IBE_R (*((reg32_t *)0x40024408))
350 #define GPIO_PORTE_IEV_R (*((reg32_t *)0x4002440C))
351 #define GPIO_PORTE_IM_R (*((reg32_t *)0x40024410))
352 #define GPIO_PORTE_RIS_R (*((reg32_t *)0x40024414))
353 #define GPIO_PORTE_MIS_R (*((reg32_t *)0x40024418))
354 #define GPIO_PORTE_ICR_R (*((reg32_t *)0x4002441C))
355 #define GPIO_PORTE_AFSEL_R (*((reg32_t *)0x40024420))
356 #define GPIO_PORTE_DR2R_R (*((reg32_t *)0x40024500))
357 #define GPIO_PORTE_DR4R_R (*((reg32_t *)0x40024504))
358 #define GPIO_PORTE_DR8R_R (*((reg32_t *)0x40024508))
359 #define GPIO_PORTE_ODR_R (*((reg32_t *)0x4002450C))
360 #define GPIO_PORTE_PUR_R (*((reg32_t *)0x40024510))
361 #define GPIO_PORTE_PDR_R (*((reg32_t *)0x40024514))
362 #define GPIO_PORTE_SLR_R (*((reg32_t *)0x40024518))
363 #define GPIO_PORTE_DEN_R (*((reg32_t *)0x4002451C))
364 #define GPIO_PORTE_LOCK_R (*((reg32_t *)0x40024520))
365 #define GPIO_PORTE_CR_R (*((reg32_t *)0x40024524))
369 * GPIO registers (PORTF)
372 #define GPIO_PORTF_DATA_BITS_R ((reg32_t *)0x40025000)
373 #define GPIO_PORTF_DATA_R (*((reg32_t *)0x400253FC))
374 #define GPIO_PORTF_DIR_R (*((reg32_t *)0x40025400))
375 #define GPIO_PORTF_IS_R (*((reg32_t *)0x40025404))
376 #define GPIO_PORTF_IBE_R (*((reg32_t *)0x40025408))
377 #define GPIO_PORTF_IEV_R (*((reg32_t *)0x4002540C))
378 #define GPIO_PORTF_IM_R (*((reg32_t *)0x40025410))
379 #define GPIO_PORTF_RIS_R (*((reg32_t *)0x40025414))
380 #define GPIO_PORTF_MIS_R (*((reg32_t *)0x40025418))
381 #define GPIO_PORTF_ICR_R (*((reg32_t *)0x4002541C))
382 #define GPIO_PORTF_AFSEL_R (*((reg32_t *)0x40025420))
383 #define GPIO_PORTF_DR2R_R (*((reg32_t *)0x40025500))
384 #define GPIO_PORTF_DR4R_R (*((reg32_t *)0x40025504))
385 #define GPIO_PORTF_DR8R_R (*((reg32_t *)0x40025508))
386 #define GPIO_PORTF_ODR_R (*((reg32_t *)0x4002550C))
387 #define GPIO_PORTF_PUR_R (*((reg32_t *)0x40025510))
388 #define GPIO_PORTF_PDR_R (*((reg32_t *)0x40025514))
389 #define GPIO_PORTF_SLR_R (*((reg32_t *)0x40025518))
390 #define GPIO_PORTF_DEN_R (*((reg32_t *)0x4002551C))
391 #define GPIO_PORTF_LOCK_R (*((reg32_t *)0x40025520))
392 #define GPIO_PORTF_CR_R (*((reg32_t *)0x40025524))
396 * GPIO registers (PORTG)
399 #define GPIO_PORTG_DATA_BITS_R ((reg32_t *)0x40026000)
400 #define GPIO_PORTG_DATA_R (*((reg32_t *)0x400263FC))
401 #define GPIO_PORTG_DIR_R (*((reg32_t *)0x40026400))
402 #define GPIO_PORTG_IS_R (*((reg32_t *)0x40026404))
403 #define GPIO_PORTG_IBE_R (*((reg32_t *)0x40026408))
404 #define GPIO_PORTG_IEV_R (*((reg32_t *)0x4002640C))
405 #define GPIO_PORTG_IM_R (*((reg32_t *)0x40026410))
406 #define GPIO_PORTG_RIS_R (*((reg32_t *)0x40026414))
407 #define GPIO_PORTG_MIS_R (*((reg32_t *)0x40026418))
408 #define GPIO_PORTG_ICR_R (*((reg32_t *)0x4002641C))
409 #define GPIO_PORTG_AFSEL_R (*((reg32_t *)0x40026420))
410 #define GPIO_PORTG_DR2R_R (*((reg32_t *)0x40026500))
411 #define GPIO_PORTG_DR4R_R (*((reg32_t *)0x40026504))
412 #define GPIO_PORTG_DR8R_R (*((reg32_t *)0x40026508))
413 #define GPIO_PORTG_ODR_R (*((reg32_t *)0x4002650C))
414 #define GPIO_PORTG_PUR_R (*((reg32_t *)0x40026510))
415 #define GPIO_PORTG_PDR_R (*((reg32_t *)0x40026514))
416 #define GPIO_PORTG_SLR_R (*((reg32_t *)0x40026518))
417 #define GPIO_PORTG_DEN_R (*((reg32_t *)0x4002651C))
418 #define GPIO_PORTG_LOCK_R (*((reg32_t *)0x40026520))
419 #define GPIO_PORTG_CR_R (*((reg32_t *)0x40026524))
423 * GPIO registers (PORTH)
426 #define GPIO_PORTH_DATA_BITS_R ((reg32_t *)0x40027000)
427 #define GPIO_PORTH_DATA_R (*((reg32_t *)0x400273FC))
428 #define GPIO_PORTH_DIR_R (*((reg32_t *)0x40027400))
429 #define GPIO_PORTH_IS_R (*((reg32_t *)0x40027404))
430 #define GPIO_PORTH_IBE_R (*((reg32_t *)0x40027408))
431 #define GPIO_PORTH_IEV_R (*((reg32_t *)0x4002740C))
432 #define GPIO_PORTH_IM_R (*((reg32_t *)0x40027410))
433 #define GPIO_PORTH_RIS_R (*((reg32_t *)0x40027414))
434 #define GPIO_PORTH_MIS_R (*((reg32_t *)0x40027418))
435 #define GPIO_PORTH_ICR_R (*((reg32_t *)0x4002741C))
436 #define GPIO_PORTH_AFSEL_R (*((reg32_t *)0x40027420))
437 #define GPIO_PORTH_DR2R_R (*((reg32_t *)0x40027500))
438 #define GPIO_PORTH_DR4R_R (*((reg32_t *)0x40027504))
439 #define GPIO_PORTH_DR8R_R (*((reg32_t *)0x40027508))
440 #define GPIO_PORTH_ODR_R (*((reg32_t *)0x4002750C))
441 #define GPIO_PORTH_PUR_R (*((reg32_t *)0x40027510))
442 #define GPIO_PORTH_PDR_R (*((reg32_t *)0x40027514))
443 #define GPIO_PORTH_SLR_R (*((reg32_t *)0x40027518))
444 #define GPIO_PORTH_DEN_R (*((reg32_t *)0x4002751C))
445 #define GPIO_PORTH_LOCK_R (*((reg32_t *)0x40027520))
446 #define GPIO_PORTH_CR_R (*((reg32_t *)0x40027524))
450 * PWM registers (PWM)
453 #define PWM_CTL_R (*((reg32_t *)0x40028000))
454 #define PWM_SYNC_R (*((reg32_t *)0x40028004))
455 #define PWM_ENABLE_R (*((reg32_t *)0x40028008))
456 #define PWM_INVERT_R (*((reg32_t *)0x4002800C))
457 #define PWM_FAULT_R (*((reg32_t *)0x40028010))
458 #define PWM_INTEN_R (*((reg32_t *)0x40028014))
459 #define PWM_RIS_R (*((reg32_t *)0x40028018))
460 #define PWM_ISC_R (*((reg32_t *)0x4002801C))
461 #define PWM_STATUS_R (*((reg32_t *)0x40028020))
462 #define PWM_0_CTL_R (*((reg32_t *)0x40028040))
463 #define PWM_0_INTEN_R (*((reg32_t *)0x40028044))
464 #define PWM_0_RIS_R (*((reg32_t *)0x40028048))
465 #define PWM_0_ISC_R (*((reg32_t *)0x4002804C))
466 #define PWM_0_LOAD_R (*((reg32_t *)0x40028050))
467 #define PWM_0_COUNT_R (*((reg32_t *)0x40028054))
468 #define PWM_0_CMPA_R (*((reg32_t *)0x40028058))
469 #define PWM_0_CMPB_R (*((reg32_t *)0x4002805C))
470 #define PWM_0_GENA_R (*((reg32_t *)0x40028060))
471 #define PWM_0_GENB_R (*((reg32_t *)0x40028064))
472 #define PWM_0_DBCTL_R (*((reg32_t *)0x40028068))
473 #define PWM_0_DBRISE_R (*((reg32_t *)0x4002806C))
474 #define PWM_0_DBFALL_R (*((reg32_t *)0x40028070))
475 #define PWM_1_CTL_R (*((reg32_t *)0x40028080))
476 #define PWM_1_INTEN_R (*((reg32_t *)0x40028084))
477 #define PWM_1_RIS_R (*((reg32_t *)0x40028088))
478 #define PWM_1_ISC_R (*((reg32_t *)0x4002808C))
479 #define PWM_1_LOAD_R (*((reg32_t *)0x40028090))
480 #define PWM_1_COUNT_R (*((reg32_t *)0x40028094))
481 #define PWM_1_CMPA_R (*((reg32_t *)0x40028098))
482 #define PWM_1_CMPB_R (*((reg32_t *)0x4002809C))
483 #define PWM_1_GENA_R (*((reg32_t *)0x400280A0))
484 #define PWM_1_GENB_R (*((reg32_t *)0x400280A4))
485 #define PWM_1_DBCTL_R (*((reg32_t *)0x400280A8))
486 #define PWM_1_DBRISE_R (*((reg32_t *)0x400280AC))
487 #define PWM_1_DBFALL_R (*((reg32_t *)0x400280B0))
488 #define PWM_2_CTL_R (*((reg32_t *)0x400280C0))
489 #define PWM_2_INTEN_R (*((reg32_t *)0x400280C4))
490 #define PWM_2_RIS_R (*((reg32_t *)0x400280C8))
491 #define PWM_2_ISC_R (*((reg32_t *)0x400280CC))
492 #define PWM_2_LOAD_R (*((reg32_t *)0x400280D0))
493 #define PWM_2_COUNT_R (*((reg32_t *)0x400280D4))
494 #define PWM_2_CMPA_R (*((reg32_t *)0x400280D8))
495 #define PWM_2_CMPB_R (*((reg32_t *)0x400280DC))
496 #define PWM_2_GENA_R (*((reg32_t *)0x400280E0))
497 #define PWM_2_GENB_R (*((reg32_t *)0x400280E4))
498 #define PWM_2_DBCTL_R (*((reg32_t *)0x400280E8))
499 #define PWM_2_DBRISE_R (*((reg32_t *)0x400280EC))
500 #define PWM_2_DBFALL_R (*((reg32_t *)0x400280F0))
504 * QEI registers (QEI0)
507 #define QEI0_CTL_R (*((reg32_t *)0x4002C000))
508 #define QEI0_STAT_R (*((reg32_t *)0x4002C004))
509 #define QEI0_POS_R (*((reg32_t *)0x4002C008))
510 #define QEI0_MAXPOS_R (*((reg32_t *)0x4002C00C))
511 #define QEI0_LOAD_R (*((reg32_t *)0x4002C010))
512 #define QEI0_TIME_R (*((reg32_t *)0x4002C014))
513 #define QEI0_COUNT_R (*((reg32_t *)0x4002C018))
514 #define QEI0_SPEED_R (*((reg32_t *)0x4002C01C))
515 #define QEI0_INTEN_R (*((reg32_t *)0x4002C020))
516 #define QEI0_RIS_R (*((reg32_t *)0x4002C024))
517 #define QEI0_ISC_R (*((reg32_t *)0x4002C028))
521 * QEI registers (QEI1)
524 #define QEI1_CTL_R (*((reg32_t *)0x4002D000))
525 #define QEI1_STAT_R (*((reg32_t *)0x4002D004))
526 #define QEI1_POS_R (*((reg32_t *)0x4002D008))
527 #define QEI1_MAXPOS_R (*((reg32_t *)0x4002D00C))
528 #define QEI1_LOAD_R (*((reg32_t *)0x4002D010))
529 #define QEI1_TIME_R (*((reg32_t *)0x4002D014))
530 #define QEI1_COUNT_R (*((reg32_t *)0x4002D018))
531 #define QEI1_SPEED_R (*((reg32_t *)0x4002D01C))
532 #define QEI1_INTEN_R (*((reg32_t *)0x4002D020))
533 #define QEI1_RIS_R (*((reg32_t *)0x4002D024))
534 #define QEI1_ISC_R (*((reg32_t *)0x4002D028))
538 * Timer registers (TIMER0)
541 #define TIMER0_CFG_R (*((reg32_t *)0x40030000))
542 #define TIMER0_TAMR_R (*((reg32_t *)0x40030004))
543 #define TIMER0_TBMR_R (*((reg32_t *)0x40030008))
544 #define TIMER0_CTL_R (*((reg32_t *)0x4003000C))
545 #define TIMER0_IMR_R (*((reg32_t *)0x40030018))
546 #define TIMER0_RIS_R (*((reg32_t *)0x4003001C))
547 #define TIMER0_MIS_R (*((reg32_t *)0x40030020))
548 #define TIMER0_ICR_R (*((reg32_t *)0x40030024))
549 #define TIMER0_TAILR_R (*((reg32_t *)0x40030028))
550 #define TIMER0_TBILR_R (*((reg32_t *)0x4003002C))
551 #define TIMER0_TAMATCHR_R (*((reg32_t *)0x40030030))
552 #define TIMER0_TBMATCHR_R (*((reg32_t *)0x40030034))
553 #define TIMER0_TAPR_R (*((reg32_t *)0x40030038))
554 #define TIMER0_TBPR_R (*((reg32_t *)0x4003003C))
555 #define TIMER0_TAPMR_R (*((reg32_t *)0x40030040))
556 #define TIMER0_TBPMR_R (*((reg32_t *)0x40030044))
557 #define TIMER0_TAR_R (*((reg32_t *)0x40030048))
558 #define TIMER0_TBR_R (*((reg32_t *)0x4003004C))
562 * Timer registers (TIMER1)
565 #define TIMER1_CFG_R (*((reg32_t *)0x40031000))
566 #define TIMER1_TAMR_R (*((reg32_t *)0x40031004))
567 #define TIMER1_TBMR_R (*((reg32_t *)0x40031008))
568 #define TIMER1_CTL_R (*((reg32_t *)0x4003100C))
569 #define TIMER1_IMR_R (*((reg32_t *)0x40031018))
570 #define TIMER1_RIS_R (*((reg32_t *)0x4003101C))
571 #define TIMER1_MIS_R (*((reg32_t *)0x40031020))
572 #define TIMER1_ICR_R (*((reg32_t *)0x40031024))
573 #define TIMER1_TAILR_R (*((reg32_t *)0x40031028))
574 #define TIMER1_TBILR_R (*((reg32_t *)0x4003102C))
575 #define TIMER1_TAMATCHR_R (*((reg32_t *)0x40031030))
576 #define TIMER1_TBMATCHR_R (*((reg32_t *)0x40031034))
577 #define TIMER1_TAPR_R (*((reg32_t *)0x40031038))
578 #define TIMER1_TBPR_R (*((reg32_t *)0x4003103C))
579 #define TIMER1_TAPMR_R (*((reg32_t *)0x40031040))
580 #define TIMER1_TBPMR_R (*((reg32_t *)0x40031044))
581 #define TIMER1_TAR_R (*((reg32_t *)0x40031048))
582 #define TIMER1_TBR_R (*((reg32_t *)0x4003104C))
586 * Timer registers (TIMER2)
589 #define TIMER2_CFG_R (*((reg32_t *)0x40032000))
590 #define TIMER2_TAMR_R (*((reg32_t *)0x40032004))
591 #define TIMER2_TBMR_R (*((reg32_t *)0x40032008))
592 #define TIMER2_CTL_R (*((reg32_t *)0x4003200C))
593 #define TIMER2_IMR_R (*((reg32_t *)0x40032018))
594 #define TIMER2_RIS_R (*((reg32_t *)0x4003201C))
595 #define TIMER2_MIS_R (*((reg32_t *)0x40032020))
596 #define TIMER2_ICR_R (*((reg32_t *)0x40032024))
597 #define TIMER2_TAILR_R (*((reg32_t *)0x40032028))
598 #define TIMER2_TBILR_R (*((reg32_t *)0x4003202C))
599 #define TIMER2_TAMATCHR_R (*((reg32_t *)0x40032030))
600 #define TIMER2_TBMATCHR_R (*((reg32_t *)0x40032034))
601 #define TIMER2_TAPR_R (*((reg32_t *)0x40032038))
602 #define TIMER2_TBPR_R (*((reg32_t *)0x4003203C))
603 #define TIMER2_TAPMR_R (*((reg32_t *)0x40032040))
604 #define TIMER2_TBPMR_R (*((reg32_t *)0x40032044))
605 #define TIMER2_TAR_R (*((reg32_t *)0x40032048))
606 #define TIMER2_TBR_R (*((reg32_t *)0x4003204C))
610 * Timer registers (TIMER3)
613 #define TIMER3_CFG_R (*((reg32_t *)0x40033000))
614 #define TIMER3_TAMR_R (*((reg32_t *)0x40033004))
615 #define TIMER3_TBMR_R (*((reg32_t *)0x40033008))
616 #define TIMER3_CTL_R (*((reg32_t *)0x4003300C))
617 #define TIMER3_IMR_R (*((reg32_t *)0x40033018))
618 #define TIMER3_RIS_R (*((reg32_t *)0x4003301C))
619 #define TIMER3_MIS_R (*((reg32_t *)0x40033020))
620 #define TIMER3_ICR_R (*((reg32_t *)0x40033024))
621 #define TIMER3_TAILR_R (*((reg32_t *)0x40033028))
622 #define TIMER3_TBILR_R (*((reg32_t *)0x4003302C))
623 #define TIMER3_TAMATCHR_R (*((reg32_t *)0x40033030))
624 #define TIMER3_TBMATCHR_R (*((reg32_t *)0x40033034))
625 #define TIMER3_TAPR_R (*((reg32_t *)0x40033038))
626 #define TIMER3_TBPR_R (*((reg32_t *)0x4003303C))
627 #define TIMER3_TAPMR_R (*((reg32_t *)0x40033040))
628 #define TIMER3_TBPMR_R (*((reg32_t *)0x40033044))
629 #define TIMER3_TAR_R (*((reg32_t *)0x40033048))
630 #define TIMER3_TBR_R (*((reg32_t *)0x4003304C))
634 * ADC registers (ADC0)
637 #define ADC0_ACTSS_R (*((reg32_t *)0x40038000))
638 #define ADC0_RIS_R (*((reg32_t *)0x40038004))
639 #define ADC0_IM_R (*((reg32_t *)0x40038008))
640 #define ADC0_ISC_R (*((reg32_t *)0x4003800C))
641 #define ADC0_OSTAT_R (*((reg32_t *)0x40038010))
642 #define ADC0_EMUX_R (*((reg32_t *)0x40038014))
643 #define ADC0_USTAT_R (*((reg32_t *)0x40038018))
644 #define ADC0_SSPRI_R (*((reg32_t *)0x40038020))
645 #define ADC0_PSSI_R (*((reg32_t *)0x40038028))
646 #define ADC0_SAC_R (*((reg32_t *)0x40038030))
647 #define ADC0_SSMUX0_R (*((reg32_t *)0x40038040))
648 #define ADC0_SSCTL0_R (*((reg32_t *)0x40038044))
649 #define ADC0_SSFIFO0_R (*((reg32_t *)0x40038048))
650 #define ADC0_SSFSTAT0_R (*((reg32_t *)0x4003804C))
651 #define ADC0_SSMUX1_R (*((reg32_t *)0x40038060))
652 #define ADC0_SSCTL1_R (*((reg32_t *)0x40038064))
653 #define ADC0_SSFIFO1_R (*((reg32_t *)0x40038068))
654 #define ADC0_SSFSTAT1_R (*((reg32_t *)0x4003806C))
655 #define ADC0_SSMUX2_R (*((reg32_t *)0x40038080))
656 #define ADC0_SSCTL2_R (*((reg32_t *)0x40038084))
657 #define ADC0_SSFIFO2_R (*((reg32_t *)0x40038088))
658 #define ADC0_SSFSTAT2_R (*((reg32_t *)0x4003808C))
659 #define ADC0_SSMUX3_R (*((reg32_t *)0x400380A0))
660 #define ADC0_SSCTL3_R (*((reg32_t *)0x400380A4))
661 #define ADC0_SSFIFO3_R (*((reg32_t *)0x400380A8))
662 #define ADC0_SSFSTAT3_R (*((reg32_t *)0x400380AC))
663 #define ADC0_TMLB_R (*((reg32_t *)0x40038100))
667 * Comparator registers (COMP)
670 #define COMP_ACMIS_R (*((reg32_t *)0x4003C000))
671 #define COMP_ACRIS_R (*((reg32_t *)0x4003C004))
672 #define COMP_ACINTEN_R (*((reg32_t *)0x4003C008))
673 #define COMP_ACREFCTL_R (*((reg32_t *)0x4003C010))
674 #define COMP_ACSTAT0_R (*((reg32_t *)0x4003C020))
675 #define COMP_ACCTL0_R (*((reg32_t *)0x4003C024))
676 #define COMP_ACSTAT1_R (*((reg32_t *)0x4003C040))
677 #define COMP_ACCTL1_R (*((reg32_t *)0x4003C044))
678 #define COMP_ACSTAT2_R (*((reg32_t *)0x4003C060))
679 #define COMP_ACCTL2_R (*((reg32_t *)0x4003C064))
683 * Hibernation module registers (HIB)
686 #define HIB_RTCC_R (*((reg32_t *)0x400FC000))
687 #define HIB_RTCM0_R (*((reg32_t *)0x400FC004))
688 #define HIB_RTCM1_R (*((reg32_t *)0x400FC008))
689 #define HIB_RTCLD_R (*((reg32_t *)0x400FC00C))
690 #define HIB_CTL_R (*((reg32_t *)0x400FC010))
691 #define HIB_IM_R (*((reg32_t *)0x400FC014))
692 #define HIB_RIS_R (*((reg32_t *)0x400FC018))
693 #define HIB_MIS_R (*((reg32_t *)0x400FC01C))
694 #define HIB_IC_R (*((reg32_t *)0x400FC020))
695 #define HIB_RTCT_R (*((reg32_t *)0x400FC024))
696 #define HIB_DATA_R (*((reg32_t *)0x400FC030))
700 * FLASH registers (FLASH CTRL)
703 #define FLASH_FMA_R (*((reg32_t *)0x400FD000))
704 #define FLASH_FMD_R (*((reg32_t *)0x400FD004))
705 #define FLASH_FMC_R (*((reg32_t *)0x400FD008))
706 #define FLASH_FCRIS_R (*((reg32_t *)0x400FD00C))
707 #define FLASH_FCIM_R (*((reg32_t *)0x400FD010))
708 #define FLASH_FCMISC_R (*((reg32_t *)0x400FD014))
709 #define FLASH_USECRL_R (*((reg32_t *)0x400FE140))
710 #define FLASH_USERDBG_R (*((reg32_t *)0x400FE1D0))
711 #define FLASH_USERREG0_R (*((reg32_t *)0x400FE1E0))
712 #define FLASH_USERREG1_R (*((reg32_t *)0x400FE1E4))
713 #define FLASH_FMPRE0_R (*((reg32_t *)0x400FE200))
714 #define FLASH_FMPRE1_R (*((reg32_t *)0x400FE204))
715 #define FLASH_FMPRE2_R (*((reg32_t *)0x400FE208))
716 #define FLASH_FMPRE3_R (*((reg32_t *)0x400FE20C))
717 #define FLASH_FMPPE0_R (*((reg32_t *)0x400FE400))
718 #define FLASH_FMPPE1_R (*((reg32_t *)0x400FE404))
719 #define FLASH_FMPPE2_R (*((reg32_t *)0x400FE408))
720 #define FLASH_FMPPE3_R (*((reg32_t *)0x400FE40C))
724 * System Control registers (SYSCTL)
727 #define SYSCTL_DID0_R (*((reg32_t *)0x400FE000))
728 #define SYSCTL_DID1_R (*((reg32_t *)0x400FE004))
729 #define SYSCTL_DC0_R (*((reg32_t *)0x400FE008))
730 #define SYSCTL_DC1_R (*((reg32_t *)0x400FE010))
731 #define SYSCTL_DC2_R (*((reg32_t *)0x400FE014))
732 #define SYSCTL_DC3_R (*((reg32_t *)0x400FE018))
733 #define SYSCTL_DC4_R (*((reg32_t *)0x400FE01C))
734 #define SYSCTL_PBORCTL_R (*((reg32_t *)0x400FE030))
735 #define SYSCTL_LDOPCTL_R (*((reg32_t *)0x400FE034))
736 #define SYSCTL_SRCR0_R (*((reg32_t *)0x400FE040))
737 #define SYSCTL_SRCR1_R (*((reg32_t *)0x400FE044))
738 #define SYSCTL_SRCR2_R (*((reg32_t *)0x400FE048))
739 #define SYSCTL_RIS_R (*((reg32_t *)0x400FE050))
740 #define SYSCTL_IMC_R (*((reg32_t *)0x400FE054))
741 #define SYSCTL_MISC_R (*((reg32_t *)0x400FE058))
742 #define SYSCTL_RESC_R (*((reg32_t *)0x400FE05C))
743 #define SYSCTL_RCC_R (*((reg32_t *)0x400FE060))
744 #define SYSCTL_PLLCFG_R (*((reg32_t *)0x400FE064))
745 #define SYSCTL_RCC2_R (*((reg32_t *)0x400FE070))
746 #define SYSCTL_RCGC0_R (*((reg32_t *)0x400FE100))
747 #define SYSCTL_RCGC1_R (*((reg32_t *)0x400FE104))
748 #define SYSCTL_RCGC2_R (*((reg32_t *)0x400FE108))
749 #define SYSCTL_SCGC0_R (*((reg32_t *)0x400FE110))
750 #define SYSCTL_SCGC1_R (*((reg32_t *)0x400FE114))
751 #define SYSCTL_SCGC2_R (*((reg32_t *)0x400FE118))
752 #define SYSCTL_DCGC0_R (*((reg32_t *)0x400FE120))
753 #define SYSCTL_DCGC1_R (*((reg32_t *)0x400FE124))
754 #define SYSCTL_DCGC2_R (*((reg32_t *)0x400FE128))
755 #define SYSCTL_DSLPCLKCFG_R (*((reg32_t *)0x400FE144))
759 * NVIC registers (NVIC)
762 #define NVIC_INT_TYPE_R (*((reg32_t *)0xE000E004))
763 #define NVIC_ST_CTRL_R (*((reg32_t *)0xE000E010))
764 #define NVIC_ST_RELOAD_R (*((reg32_t *)0xE000E014))
765 #define NVIC_ST_CURRENT_R (*((reg32_t *)0xE000E018))
766 #define NVIC_ST_CAL_R (*((reg32_t *)0xE000E01C))
767 #define NVIC_EN0_R (*((reg32_t *)0xE000E100))
768 #define NVIC_EN1_R (*((reg32_t *)0xE000E104))
769 #define NVIC_DIS0_R (*((reg32_t *)0xE000E180))
770 #define NVIC_DIS1_R (*((reg32_t *)0xE000E184))
771 #define NVIC_PEND0_R (*((reg32_t *)0xE000E200))
772 #define NVIC_PEND1_R (*((reg32_t *)0xE000E204))
773 #define NVIC_UNPEND0_R (*((reg32_t *)0xE000E280))
774 #define NVIC_UNPEND1_R (*((reg32_t *)0xE000E284))
775 #define NVIC_ACTIVE0_R (*((reg32_t *)0xE000E300))
776 #define NVIC_ACTIVE1_R (*((reg32_t *)0xE000E304))
777 #define NVIC_PRI0_R (*((reg32_t *)0xE000E400))
778 #define NVIC_PRI1_R (*((reg32_t *)0xE000E404))
779 #define NVIC_PRI2_R (*((reg32_t *)0xE000E408))
780 #define NVIC_PRI3_R (*((reg32_t *)0xE000E40C))
781 #define NVIC_PRI4_R (*((reg32_t *)0xE000E410))
782 #define NVIC_PRI5_R (*((reg32_t *)0xE000E414))
783 #define NVIC_PRI6_R (*((reg32_t *)0xE000E418))
784 #define NVIC_PRI7_R (*((reg32_t *)0xE000E41C))
785 #define NVIC_PRI8_R (*((reg32_t *)0xE000E420))
786 #define NVIC_PRI9_R (*((reg32_t *)0xE000E424))
787 #define NVIC_PRI10_R (*((reg32_t *)0xE000E428))
788 #define NVIC_CPUID_R (*((reg32_t *)0xE000ED00))
789 #define NVIC_INT_CTRL_R (*((reg32_t *)0xE000ED04))
790 #define NVIC_VTABLE_R (*((reg32_t *)0xE000ED08))
791 #define NVIC_APINT_R (*((reg32_t *)0xE000ED0C))
792 #define NVIC_SYS_CTRL_R (*((reg32_t *)0xE000ED10))
793 #define NVIC_CFG_CTRL_R (*((reg32_t *)0xE000ED14))
794 #define NVIC_SYS_PRI1_R (*((reg32_t *)0xE000ED18))
795 #define NVIC_SYS_PRI2_R (*((reg32_t *)0xE000ED1C))
796 #define NVIC_SYS_PRI3_R (*((reg32_t *)0xE000ED20))
797 #define NVIC_SYS_HND_CTRL_R (*((reg32_t *)0xE000ED24))
798 #define NVIC_FAULT_STAT_R (*((reg32_t *)0xE000ED28))
799 #define NVIC_HFAULT_STAT_R (*((reg32_t *)0xE000ED2C))
800 #define NVIC_DEBUG_STAT_R (*((reg32_t *)0xE000ED30))
801 #define NVIC_MM_ADDR_R (*((reg32_t *)0xE000ED34))
802 #define NVIC_FAULT_ADDR_R (*((reg32_t *)0xE000ED38))
803 #define NVIC_MPU_TYPE_R (*((reg32_t *)0xE000ED90))
804 #define NVIC_MPU_CTRL_R (*((reg32_t *)0xE000ED94))
805 #define NVIC_MPU_NUMBER_R (*((reg32_t *)0xE000ED98))
806 #define NVIC_MPU_BASE_R (*((reg32_t *)0xE000ED9C))
807 #define NVIC_MPU_ATTR_R (*((reg32_t *)0xE000EDA0))
808 #define NVIC_DBG_CTRL_R (*((reg32_t *)0xE000EDF0))
809 #define NVIC_DBG_XFER_R (*((reg32_t *)0xE000EDF4))
810 #define NVIC_DBG_DATA_R (*((reg32_t *)0xE000EDF8))
811 #define NVIC_DBG_INT_R (*((reg32_t *)0xE000EDFC))
812 #define NVIC_SW_TRIG_R (*((reg32_t *)0xE000EF00))
816 * The following are defines for the bit fields in the WDT_O_LOAD register.
819 #define WDT_LOAD_M 0xFFFFFFFF ///< Watchdog Load Value
824 * The following are defines for the bit fields in the WDT_O_VALUE register.
827 #define WDT_VALUE_M 0xFFFFFFFF ///< Watchdog Value
828 #define WDT_VALUE_S 0
832 * The following are defines for the bit fields in the WDT_O_CTL register.
835 #define WDT_CTL_RESEN 0x00000002 ///< Watchdog Reset Enable
836 #define WDT_CTL_INTEN 0x00000001 ///< Watchdog Interrupt Enable
840 * The following are defines for the bit fields in the WDT_O_ICR register.
843 #define WDT_ICR_M 0xFFFFFFFF ///< Watchdog Interrupt Clear
848 * The following are defines for the bit fields in the WDT_O_RIS register.
851 #define WDT_RIS_WDTRIS 0x00000001 ///< Watchdog Raw Interrupt Status
855 * The following are defines for the bit fields in the WDT_O_MIS register.
858 #define WDT_MIS_WDTMIS 0x00000001 ///< Watchdog Masked Interrupt Status
862 * The following are defines for the bit fields in the WDT_O_TEST register.
865 #define WDT_TEST_STALL 0x00000100 ///< Watchdog Stall Enable
869 * The following are defines for the bit fields in the WDT_O_LOCK register.
872 #define WDT_LOCK_M 0xFFFFFFFF ///< Watchdog Lock
873 #define WDT_LOCK_UNLOCKED 0x00000000 ///< Unlocked
874 #define WDT_LOCK_LOCKED 0x00000001 ///< Locked
875 #define WDT_LOCK_UNLOCK 0x1ACCE551 ///< Unlocks the watchdog timer
879 * The following are defines for the bit fields in the GPIO_O_LOCK register.
882 #define GPIO_LOCK_M 0xFFFFFFFF ///< GPIO Lock
883 #define GPIO_LOCK_UNLOCKED 0x00000000 ///< The GPIOCR register is unlocked
884 ///< and may be modified
885 #define GPIO_LOCK_LOCKED 0x00000001 ///< The GPIOCR register is locked
886 ///< and may not be modified
887 #define GPIO_LOCK_KEY 0x1ACCE551 ///< Unlocks the GPIO_CR register
891 * The following are defines for the bit fields in the SSI_O_CR0 register.
894 #define SSI_CR0_SCR_M 0x0000FF00 ///< SSI Serial Clock Rate
895 #define SSI_CR0_SPH 0x00000080 ///< SSI Serial Clock Phase
896 #define SSI_CR0_SPO 0x00000040 ///< SSI Serial Clock Polarity
897 #define SSI_CR0_FRF_M 0x00000030 ///< SSI Frame Format Select
898 #define SSI_CR0_FRF_MOTO 0x00000000 ///< Freescale SPI Frame Format
899 #define SSI_CR0_FRF_TI 0x00000010 ///< Texas Instruments Synchronous
900 ///< Serial Frame Format
901 #define SSI_CR0_FRF_NMW 0x00000020 ///< MICROWIRE Frame Format
902 #define SSI_CR0_DSS_M 0x0000000F ///< SSI Data Size Select
903 #define SSI_CR0_DSS_4 0x00000003 ///< 4-bit data
904 #define SSI_CR0_DSS_5 0x00000004 ///< 5-bit data
905 #define SSI_CR0_DSS_6 0x00000005 ///< 6-bit data
906 #define SSI_CR0_DSS_7 0x00000006 ///< 7-bit data
907 #define SSI_CR0_DSS_8 0x00000007 ///< 8-bit data
908 #define SSI_CR0_DSS_9 0x00000008 ///< 9-bit data
909 #define SSI_CR0_DSS_10 0x00000009 ///< 10-bit data
910 #define SSI_CR0_DSS_11 0x0000000A ///< 11-bit data
911 #define SSI_CR0_DSS_12 0x0000000B ///< 12-bit data
912 #define SSI_CR0_DSS_13 0x0000000C ///< 13-bit data
913 #define SSI_CR0_DSS_14 0x0000000D ///< 14-bit data
914 #define SSI_CR0_DSS_15 0x0000000E ///< 15-bit data
915 #define SSI_CR0_DSS_16 0x0000000F ///< 16-bit data
916 #define SSI_CR0_SCR_S 8
920 * The following are defines for the bit fields in the SSI_O_CR1 register.
923 #define SSI_CR1_SOD 0x00000008 ///< SSI Slave Mode Output Disable
924 #define SSI_CR1_MS 0x00000004 ///< SSI Master/Slave Select
925 #define SSI_CR1_SSE 0x00000002 ///< SSI Synchronous Serial Port
927 #define SSI_CR1_LBM 0x00000001 ///< SSI Loopback Mode
931 * The following are defines for the bit fields in the SSI_O_DR register.
934 #define SSI_DR_DATA_M 0x0000FFFF ///< SSI Receive/Transmit Data
935 #define SSI_DR_DATA_S 0
939 * The following are defines for the bit fields in the SSI_O_SR register.
942 #define SSI_SR_BSY 0x00000010 ///< SSI Busy Bit
943 #define SSI_SR_RFF 0x00000008 ///< SSI Receive FIFO Full
944 #define SSI_SR_RNE 0x00000004 ///< SSI Receive FIFO Not Empty
945 #define SSI_SR_TNF 0x00000002 ///< SSI Transmit FIFO Not Full
946 #define SSI_SR_TFE 0x00000001 ///< SSI Transmit FIFO Empty
950 * The following are defines for the bit fields in the SSI_O_CPSR register.
953 #define SSI_CPSR_CPSDVSR_M 0x000000FF ///< SSI Clock Prescale Divisor
954 #define SSI_CPSR_CPSDVSR_S 0
958 * The following are defines for the bit fields in the SSI_O_IM register.
961 #define SSI_IM_TXIM 0x00000008 ///< SSI Transmit FIFO Interrupt Mask
962 #define SSI_IM_RXIM 0x00000004 ///< SSI Receive FIFO Interrupt Mask
963 #define SSI_IM_RTIM 0x00000002 ///< SSI Receive Time-Out Interrupt
965 #define SSI_IM_RORIM 0x00000001 ///< SSI Receive Overrun Interrupt
970 * The following are defines for the bit fields in the SSI_O_RIS register.
973 #define SSI_RIS_TXRIS 0x00000008 ///< SSI Transmit FIFO Raw Interrupt
975 #define SSI_RIS_RXRIS 0x00000004 ///< SSI Receive FIFO Raw Interrupt
977 #define SSI_RIS_RTRIS 0x00000002 ///< SSI Receive Time-Out Raw
978 ///< Interrupt Status
979 #define SSI_RIS_RORRIS 0x00000001 ///< SSI Receive Overrun Raw
980 ///< Interrupt Status
984 * The following are defines for the bit fields in the SSI_O_MIS register.
987 #define SSI_MIS_TXMIS 0x00000008 ///< SSI Transmit FIFO Masked
988 ///< Interrupt Status
989 #define SSI_MIS_RXMIS 0x00000004 ///< SSI Receive FIFO Masked
990 ///< Interrupt Status
991 #define SSI_MIS_RTMIS 0x00000002 ///< SSI Receive Time-Out Masked
992 ///< Interrupt Status
993 #define SSI_MIS_RORMIS 0x00000001 ///< SSI Receive Overrun Masked
994 ///< Interrupt Status
998 * The following are defines for the bit fields in the SSI_O_ICR register.
1001 #define SSI_ICR_RTIC 0x00000002 ///< SSI Receive Time-Out Interrupt
1003 #define SSI_ICR_RORIC 0x00000001 ///< SSI Receive Overrun Interrupt
1008 * The following are defines for the bit fields in the UART_O_DR register.
1011 #define UART_DR_OE 0x00000800 ///< UART Overrun Error
1012 #define UART_DR_BE 0x00000400 ///< UART Break Error
1013 #define UART_DR_PE 0x00000200 ///< UART Parity Error
1014 #define UART_DR_FE 0x00000100 ///< UART Framing Error
1015 #define UART_DR_DATA_M 0x000000FF ///< Data Transmitted or Received
1016 #define UART_DR_DATA_S 0
1020 * The following are defines for the bit fields in the UART_O_RSR register.
1023 #define UART_RSR_OE 0x00000008 ///< UART Overrun Error
1024 #define UART_RSR_BE 0x00000004 ///< UART Break Error
1025 #define UART_RSR_PE 0x00000002 ///< UART Parity Error
1026 #define UART_RSR_FE 0x00000001 ///< UART Framing Error
1030 * The following are defines for the bit fields in the UART_O_ECR register.
1033 #define UART_ECR_DATA_M 0x000000FF ///< Error Clear
1034 #define UART_ECR_DATA_S 0
1038 * The following are defines for the bit fields in the UART_O_FR register.
1041 #define UART_FR_TXFE 0x00000080 ///< UART Transmit FIFO Empty
1042 #define UART_FR_RXFF 0x00000040 ///< UART Receive FIFO Full
1043 #define UART_FR_TXFF 0x00000020 ///< UART Transmit FIFO Full
1044 #define UART_FR_RXFE 0x00000010 ///< UART Receive FIFO Empty
1045 #define UART_FR_BUSY 0x00000008 ///< UART Busy
1049 * The following are defines for the bit fields in the UART_O_ILPR register.
1052 #define UART_ILPR_ILPDVSR_M 0x000000FF ///< IrDA Low-Power Divisor
1053 #define UART_ILPR_ILPDVSR_S 0
1057 * The following are defines for the bit fields in the UART_O_IBRD register.
1060 #define UART_IBRD_DIVINT_M 0x0000FFFF ///< Integer Baud-Rate Divisor
1061 #define UART_IBRD_DIVINT_S 0
1065 * The following are defines for the bit fields in the UART_O_FBRD register.
1068 #define UART_FBRD_DIVFRAC_M 0x0000003F ///< Fractional Baud-Rate Divisor
1069 #define UART_FBRD_DIVFRAC_S 0
1073 * The following are defines for the bit fields in the UART_O_LCRH register.
1076 #define UART_LCRH_SPS 0x00000080 ///< UART Stick Parity Select
1077 #define UART_LCRH_WLEN_M 0x00000060 ///< UART Word Length
1078 #define UART_LCRH_WLEN_5 0x00000000 ///< 5 bits (default)
1079 #define UART_LCRH_WLEN_6 0x00000020 ///< 6 bits
1080 #define UART_LCRH_WLEN_7 0x00000040 ///< 7 bits
1081 #define UART_LCRH_WLEN_8 0x00000060 ///< 8 bits
1082 #define UART_LCRH_FEN 0x00000010 ///< UART Enable FIFOs
1083 #define UART_LCRH_STP2 0x00000008 ///< UART Two Stop Bits Select
1084 #define UART_LCRH_EPS 0x00000004 ///< UART Even Parity Select
1085 #define UART_LCRH_PEN 0x00000002 ///< UART Parity Enable
1086 #define UART_LCRH_BRK 0x00000001 ///< UART Send Break
1090 * The following are defines for the bit fields in the UART_O_CTL register.
1093 #define UART_CTL_RXE 0x00000200 ///< UART Receive Enable
1094 #define UART_CTL_TXE 0x00000100 ///< UART Transmit Enable
1095 #define UART_CTL_LBE 0x00000080 ///< UART Loop Back Enable
1096 #define UART_CTL_SIRLP 0x00000004 ///< UART SIR Low-Power Mode
1097 #define UART_CTL_SIREN 0x00000002 ///< UART SIR Enable
1098 #define UART_CTL_UARTEN 0x00000001 ///< UART Enable
1102 * The following are defines for the bit fields in the UART_O_IFLS register.
1105 #define UART_IFLS_RX_M 0x00000038 ///< UART Receive Interrupt FIFO
1107 #define UART_IFLS_RX1_8 0x00000000 ///< RX FIFO >= 1/8 full
1108 #define UART_IFLS_RX2_8 0x00000008 ///< RX FIFO >= 1/4 full
1109 #define UART_IFLS_RX4_8 0x00000010 ///< RX FIFO >= 1/2 full (default)
1110 #define UART_IFLS_RX6_8 0x00000018 ///< RX FIFO >= 3/4 full
1111 #define UART_IFLS_RX7_8 0x00000020 ///< RX FIFO >= 7/8 full
1112 #define UART_IFLS_TX_M 0x00000007 ///< UART Transmit Interrupt FIFO
1114 #define UART_IFLS_TX1_8 0x00000000 ///< TX FIFO <= 1/8 full
1115 #define UART_IFLS_TX2_8 0x00000001 ///< TX FIFO <= 1/4 full
1116 #define UART_IFLS_TX4_8 0x00000002 ///< TX FIFO <= 1/2 full (default)
1117 #define UART_IFLS_TX6_8 0x00000003 ///< TX FIFO <= 3/4 full
1118 #define UART_IFLS_TX7_8 0x00000004 ///< TX FIFO <= 7/8 full
1122 * The following are defines for the bit fields in the UART_O_IM register.
1125 #define UART_IM_OEIM 0x00000400 ///< UART Overrun Error Interrupt
1127 #define UART_IM_BEIM 0x00000200 ///< UART Break Error Interrupt Mask
1128 #define UART_IM_PEIM 0x00000100 ///< UART Parity Error Interrupt Mask
1129 #define UART_IM_FEIM 0x00000080 ///< UART Framing Error Interrupt
1131 #define UART_IM_RTIM 0x00000040 ///< UART Receive Time-Out Interrupt
1133 #define UART_IM_TXIM 0x00000020 ///< UART Transmit Interrupt Mask
1134 #define UART_IM_RXIM 0x00000010 ///< UART Receive Interrupt Mask
1138 * The following are defines for the bit fields in the UART_O_RIS register.
1141 #define UART_RIS_OERIS 0x00000400 ///< UART Overrun Error Raw Interrupt
1143 #define UART_RIS_BERIS 0x00000200 ///< UART Break Error Raw Interrupt
1145 #define UART_RIS_PERIS 0x00000100 ///< UART Parity Error Raw Interrupt
1147 #define UART_RIS_FERIS 0x00000080 ///< UART Framing Error Raw Interrupt
1149 #define UART_RIS_RTRIS 0x00000040 ///< UART Receive Time-Out Raw
1150 ///< Interrupt Status
1151 #define UART_RIS_TXRIS 0x00000020 ///< UART Transmit Raw Interrupt
1153 #define UART_RIS_RXRIS 0x00000010 ///< UART Receive Raw Interrupt
1158 * The following are defines for the bit fields in the UART_O_MIS register.
1161 #define UART_MIS_OEMIS 0x00000400 ///< UART Overrun Error Masked
1162 ///< Interrupt Status
1163 #define UART_MIS_BEMIS 0x00000200 ///< UART Break Error Masked
1164 ///< Interrupt Status
1165 #define UART_MIS_PEMIS 0x00000100 ///< UART Parity Error Masked
1166 ///< Interrupt Status
1167 #define UART_MIS_FEMIS 0x00000080 ///< UART Framing Error Masked
1168 ///< Interrupt Status
1169 #define UART_MIS_RTMIS 0x00000040 ///< UART Receive Time-Out Masked
1170 ///< Interrupt Status
1171 #define UART_MIS_TXMIS 0x00000020 ///< UART Transmit Masked Interrupt
1173 #define UART_MIS_RXMIS 0x00000010 ///< UART Receive Masked Interrupt
1178 * The following are defines for the bit fields in the UART_O_ICR register.
1181 #define UART_ICR_OEIC 0x00000400 ///< Overrun Error Interrupt Clear
1182 #define UART_ICR_BEIC 0x00000200 ///< Break Error Interrupt Clear
1183 #define UART_ICR_PEIC 0x00000100 ///< Parity Error Interrupt Clear
1184 #define UART_ICR_FEIC 0x00000080 ///< Framing Error Interrupt Clear
1185 #define UART_ICR_RTIC 0x00000040 ///< Receive Time-Out Interrupt Clear
1186 #define UART_ICR_TXIC 0x00000020 ///< Transmit Interrupt Clear
1187 #define UART_ICR_RXIC 0x00000010 ///< Receive Interrupt Clear
1191 * The following are defines for the bit fields in the I2C_O_MSA register.
1194 #define I2C_MSA_SA_M 0x000000FE ///< I2C Slave Address
1195 #define I2C_MSA_RS 0x00000001 ///< Receive not send
1196 #define I2C_MSA_SA_S 1
1200 * The following are defines for the bit fields in the I2C_O_SOAR register.
1203 #define I2C_SOAR_OAR_M 0x0000007F ///< I2C Slave Own Address
1204 #define I2C_SOAR_OAR_S 0
1208 * The following are defines for the bit fields in the I2C_O_SCSR register.
1211 #define I2C_SCSR_FBR 0x00000004 ///< First Byte Received
1212 #define I2C_SCSR_TREQ 0x00000002 ///< Transmit Request
1213 #define I2C_SCSR_DA 0x00000001 ///< Device Active
1214 #define I2C_SCSR_RREQ 0x00000001 ///< Receive Request
1218 * The following are defines for the bit fields in the I2C_O_MCS register.
1221 #define I2C_MCS_BUSBSY 0x00000040 ///< Bus Busy
1222 #define I2C_MCS_IDLE 0x00000020 ///< I2C Idle
1223 #define I2C_MCS_ARBLST 0x00000010 ///< Arbitration Lost
1224 #define I2C_MCS_ACK 0x00000008 ///< Data Acknowledge Enable
1225 #define I2C_MCS_DATACK 0x00000008 ///< Acknowledge Data
1226 #define I2C_MCS_ADRACK 0x00000004 ///< Acknowledge Address
1227 #define I2C_MCS_STOP 0x00000004 ///< Generate STOP
1228 #define I2C_MCS_START 0x00000002 ///< Generate START
1229 #define I2C_MCS_ERROR 0x00000002 ///< Error
1230 #define I2C_MCS_RUN 0x00000001 ///< I2C Master Enable
1231 #define I2C_MCS_BUSY 0x00000001 ///< I2C Busy
1235 * The following are defines for the bit fields in the I2C_O_SDR register.
1238 #define I2C_SDR_DATA_M 0x000000FF ///< Data for Transfer
1239 #define I2C_SDR_DATA_S 0
1243 * The following are defines for the bit fields in the I2C_O_MDR register.
1246 #define I2C_MDR_DATA_M 0x000000FF ///< Data Transferred
1247 #define I2C_MDR_DATA_S 0
1251 * The following are defines for the bit fields in the I2C_O_MTPR register.
1254 #define I2C_MTPR_TPR_M 0x000000FF ///< SCL Clock Period
1255 #define I2C_MTPR_TPR_S 0
1259 * The following are defines for the bit fields in the I2C_O_SIMR register.
1262 #define I2C_SIMR_DATAIM 0x00000001 ///< Data Interrupt Mask
1266 * The following are defines for the bit fields in the I2C_O_SRIS register.
1269 #define I2C_SRIS_DATARIS 0x00000001 ///< Data Raw Interrupt Status
1273 * The following are defines for the bit fields in the I2C_O_MIMR register.
1276 #define I2C_MIMR_IM 0x00000001 ///< Interrupt Mask
1280 * The following are defines for the bit fields in the I2C_O_MRIS register.
1283 #define I2C_MRIS_RIS 0x00000001 ///< Raw Interrupt Status
1287 * The following are defines for the bit fields in the I2C_O_SMIS register.
1290 #define I2C_SMIS_DATAMIS 0x00000001 ///< Data Masked Interrupt Status
1294 * The following are defines for the bit fields in the I2C_O_SICR register.
1297 #define I2C_SICR_DATAIC 0x00000001 ///< Data Interrupt Clear
1301 * The following are defines for the bit fields in the I2C_O_MMIS register.
1304 #define I2C_MMIS_MIS 0x00000001 ///< Masked Interrupt Status
1308 * The following are defines for the bit fields in the I2C_O_MICR register.
1311 #define I2C_MICR_IC 0x00000001 ///< Interrupt Clear
1315 * The following are defines for the bit fields in the I2C_O_MCR register.
1318 #define I2C_MCR_SFE 0x00000020 ///< I2C Slave Function Enable
1319 #define I2C_MCR_MFE 0x00000010 ///< I2C Master Function Enable
1320 #define I2C_MCR_LPBK 0x00000001 ///< I2C Loopback
1324 * The following are defines for the bit fields in the PWM_O_CTL register.
1327 #define PWM_CTL_GLOBALSYNC2 0x00000004 ///< Update PWM Generator 2
1328 #define PWM_CTL_GLOBALSYNC1 0x00000002 ///< Update PWM Generator 1
1329 #define PWM_CTL_GLOBALSYNC0 0x00000001 ///< Update PWM Generator 0
1333 * The following are defines for the bit fields in the PWM_O_SYNC register.
1336 #define PWM_SYNC_SYNC2 0x00000004 ///< Reset Generator 2 Counter
1337 #define PWM_SYNC_SYNC1 0x00000002 ///< Reset Generator 1 Counter
1338 #define PWM_SYNC_SYNC0 0x00000001 ///< Reset Generator 0 Counter
1342 * The following are defines for the bit fields in the PWM_O_ENABLE register.
1345 #define PWM_ENABLE_PWM5EN 0x00000020 ///< PWM5 Output Enable
1346 #define PWM_ENABLE_PWM4EN 0x00000010 ///< PWM4 Output Enable
1347 #define PWM_ENABLE_PWM3EN 0x00000008 ///< PWM3 Output Enable
1348 #define PWM_ENABLE_PWM2EN 0x00000004 ///< PWM2 Output Enable
1349 #define PWM_ENABLE_PWM1EN 0x00000002 ///< PWM1 Output Enable
1350 #define PWM_ENABLE_PWM0EN 0x00000001 ///< PWM0 Output Enable
1354 * The following are defines for the bit fields in the PWM_O_INVERT register.
1357 #define PWM_INVERT_PWM5INV 0x00000020 ///< Invert PWM5 Signal
1358 #define PWM_INVERT_PWM4INV 0x00000010 ///< Invert PWM4 Signal
1359 #define PWM_INVERT_PWM3INV 0x00000008 ///< Invert PWM3 Signal
1360 #define PWM_INVERT_PWM2INV 0x00000004 ///< Invert PWM2 Signal
1361 #define PWM_INVERT_PWM1INV 0x00000002 ///< Invert PWM1 Signal
1362 #define PWM_INVERT_PWM0INV 0x00000001 ///< Invert PWM0 Signal
1366 * The following are defines for the bit fields in the PWM_O_FAULT register.
1369 #define PWM_FAULT_FAULT5 0x00000020 ///< PWM5 Fault
1370 #define PWM_FAULT_FAULT4 0x00000010 ///< PWM4 Fault
1371 #define PWM_FAULT_FAULT3 0x00000008 ///< PWM3 Fault
1372 #define PWM_FAULT_FAULT2 0x00000004 ///< PWM2 Fault
1373 #define PWM_FAULT_FAULT1 0x00000002 ///< PWM1 Fault
1374 #define PWM_FAULT_FAULT0 0x00000001 ///< PWM0 Fault
1378 * The following are defines for the bit fields in the PWM_O_INTEN register.
1381 #define PWM_INTEN_INTFAULT 0x00010000 ///< Fault Interrupt Enable
1382 #define PWM_INTEN_INTPWM2 0x00000004 ///< PWM2 Interrupt Enable
1383 #define PWM_INTEN_INTPWM1 0x00000002 ///< PWM1 Interrupt Enable
1384 #define PWM_INTEN_INTPWM0 0x00000001 ///< PWM0 Interrupt Enable
1388 * The following are defines for the bit fields in the PWM_O_RIS register.
1391 #define PWM_RIS_INTFAULT 0x00010000 ///< Fault Interrupt Asserted
1392 #define PWM_RIS_INTPWM2 0x00000004 ///< PWM2 Interrupt Asserted
1393 #define PWM_RIS_INTPWM1 0x00000002 ///< PWM1 Interrupt Asserted
1394 #define PWM_RIS_INTPWM0 0x00000001 ///< PWM0 Interrupt Asserted
1398 * The following are defines for the bit fields in the PWM_O_ISC register.
1401 #define PWM_ISC_INTFAULT 0x00010000 ///< Fault Interrupt Asserted
1402 #define PWM_ISC_INTPWM2 0x00000004 ///< PWM2 Interrupt Status
1403 #define PWM_ISC_INTPWM1 0x00000002 ///< PWM1 Interrupt Status
1404 #define PWM_ISC_INTPWM0 0x00000001 ///< PWM0 Interrupt Status
1408 * The following are defines for the bit fields in the PWM_O_STATUS register.
1411 #define PWM_STATUS_FAULT 0x00000001 ///< Fault Interrupt Status
1415 * The following are defines for the bit fields in the PWM_O_X_CTL register.
1418 #define PWM_X_CTL_CMPBUPD 0x00000020 ///< Comparator B Update Mode
1419 #define PWM_X_CTL_CMPAUPD 0x00000010 ///< Comparator A Update Mode
1420 #define PWM_X_CTL_LOADUPD 0x00000008 ///< Load Register Update Mode
1421 #define PWM_X_CTL_DEBUG 0x00000004 ///< Debug Mode
1422 #define PWM_X_CTL_MODE 0x00000002 ///< Counter Mode
1423 #define PWM_X_CTL_ENABLE 0x00000001 ///< PWM Block Enable
1427 * The following are defines for the bit fields in the PWM_O_X_INTEN register.
1430 #define PWM_X_INTEN_TRCMPBD 0x00002000 ///< Trigger for Counter=PWMnCMPB
1432 #define PWM_X_INTEN_TRCMPBU 0x00001000 ///< Trigger for Counter=PWMnCMPB Up
1433 #define PWM_X_INTEN_TRCMPAD 0x00000800 ///< Trigger for Counter=PWMnCMPA
1435 #define PWM_X_INTEN_TRCMPAU 0x00000400 ///< Trigger for Counter=PWMnCMPA Up
1436 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 ///< Trigger for Counter=PWMnLOAD
1437 #define PWM_X_INTEN_TRCNTZERO 0x00000100 ///< Trigger for Counter=0
1438 #define PWM_X_INTEN_INTCMPBD 0x00000020 ///< Interrupt for Counter=PWMnCMPB
1440 #define PWM_X_INTEN_INTCMPBU 0x00000010 ///< Interrupt for Counter=PWMnCMPB
1442 #define PWM_X_INTEN_INTCMPAD 0x00000008 ///< Interrupt for Counter=PWMnCMPA
1444 #define PWM_X_INTEN_INTCMPAU 0x00000004 ///< Interrupt for Counter=PWMnCMPA
1446 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 ///< Interrupt for Counter=PWMnLOAD
1447 #define PWM_X_INTEN_INTCNTZERO 0x00000001 ///< Interrupt for Counter=0
1451 * The following are defines for the bit fields in the PWM_O_X_RIS register.
1454 #define PWM_X_RIS_INTCMPBD 0x00000020 ///< Comparator B Down Interrupt
1456 #define PWM_X_RIS_INTCMPBU 0x00000010 ///< Comparator B Up Interrupt Status
1457 #define PWM_X_RIS_INTCMPAD 0x00000008 ///< Comparator A Down Interrupt
1459 #define PWM_X_RIS_INTCMPAU 0x00000004 ///< Comparator A Up Interrupt Status
1460 #define PWM_X_RIS_INTCNTLOAD 0x00000002 ///< Counter=Load Interrupt Status
1461 #define PWM_X_RIS_INTCNTZERO 0x00000001 ///< Counter=0 Interrupt Status
1465 * The following are defines for the bit fields in the PWM_O_X_ISC register.
1468 #define PWM_X_ISC_INTCMPBD 0x00000020 ///< Comparator B Down Interrupt
1469 #define PWM_X_ISC_INTCMPBU 0x00000010 ///< Comparator B Up Interrupt
1470 #define PWM_X_ISC_INTCMPAD 0x00000008 ///< Comparator A Down Interrupt
1471 #define PWM_X_ISC_INTCMPAU 0x00000004 ///< Comparator A Up Interrupt
1472 #define PWM_X_ISC_INTCNTLOAD 0x00000002 ///< Counter=Load Interrupt
1473 #define PWM_X_ISC_INTCNTZERO 0x00000001 ///< Counter=0 Interrupt
1477 * The following are defines for the bit fields in the PWM_O_X_LOAD register.
1480 #define PWM_X_LOAD_M 0x0000FFFF ///< Counter Load Value
1481 #define PWM_X_LOAD_S 0
1485 * The following are defines for the bit fields in the PWM_O_X_COUNT register.
1488 #define PWM_X_COUNT_M 0x0000FFFF ///< Counter Value
1489 #define PWM_X_COUNT_S 0
1493 * The following are defines for the bit fields in the PWM_O_X_CMPA register.
1496 #define PWM_X_CMPA_M 0x0000FFFF ///< Comparator A Value
1497 #define PWM_X_CMPA_S 0
1501 * The following are defines for the bit fields in the PWM_O_X_CMPB register.
1504 #define PWM_X_CMPB_M 0x0000FFFF ///< Comparator B Value
1505 #define PWM_X_CMPB_S 0
1509 * The following are defines for the bit fields in the PWM_O_X_GENA register.
1512 #define PWM_X_GENA_ACTCMPBD_M 0x00000C00 ///< Action for Comparator B Down
1513 #define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 ///< Do nothing
1514 #define PWM_X_GENA_ACTCMPBD_INV 0x00000400 ///< Invert pwmA
1515 #define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 ///< Drive pwmA Low
1516 #define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 ///< Drive pwmA High
1517 #define PWM_X_GENA_ACTCMPBU_M 0x00000300 ///< Action for Comparator B Up
1518 #define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 ///< Do nothing
1519 #define PWM_X_GENA_ACTCMPBU_INV 0x00000100 ///< Invert pwmA
1520 #define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 ///< Drive pwmA Low
1521 #define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 ///< Drive pwmA High
1522 #define PWM_X_GENA_ACTCMPAD_M 0x000000C0 ///< Action for Comparator A Down
1523 #define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 ///< Do nothing
1524 #define PWM_X_GENA_ACTCMPAD_INV 0x00000040 ///< Invert pwmA
1525 #define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 ///< Drive pwmA Low
1526 #define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 ///< Drive pwmA High
1527 #define PWM_X_GENA_ACTCMPAU_M 0x00000030 ///< Action for Comparator A Up
1528 #define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 ///< Do nothing
1529 #define PWM_X_GENA_ACTCMPAU_INV 0x00000010 ///< Invert pwmA
1530 #define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 ///< Drive pwmA Low
1531 #define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 ///< Drive pwmA High
1532 #define PWM_X_GENA_ACTLOAD_M 0x0000000C ///< Action for Counter=LOAD
1533 #define PWM_X_GENA_ACTLOAD_NONE 0x00000000 ///< Do nothing
1534 #define PWM_X_GENA_ACTLOAD_INV 0x00000004 ///< Invert pwmA
1535 #define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 ///< Drive pwmA Low
1536 #define PWM_X_GENA_ACTLOAD_ONE 0x0000000C ///< Drive pwmA High
1537 #define PWM_X_GENA_ACTZERO_M 0x00000003 ///< Action for Counter=0
1538 #define PWM_X_GENA_ACTZERO_NONE 0x00000000 ///< Do nothing
1539 #define PWM_X_GENA_ACTZERO_INV 0x00000001 ///< Invert pwmA
1540 #define PWM_X_GENA_ACTZERO_ZERO 0x00000002 ///< Drive pwmA Low
1541 #define PWM_X_GENA_ACTZERO_ONE 0x00000003 ///< Drive pwmA High
1545 * The following are defines for the bit fields in the PWM_O_X_GENB register.
1548 #define PWM_X_GENB_ACTCMPBD_M 0x00000C00 ///< Action for Comparator B Down
1549 #define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 ///< Do nothing
1550 #define PWM_X_GENB_ACTCMPBD_INV 0x00000400 ///< Invert pwmB
1551 #define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 ///< Drive pwmB Low
1552 #define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 ///< Drive pwmB High
1553 #define PWM_X_GENB_ACTCMPBU_M 0x00000300 ///< Action for Comparator B Up
1554 #define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 ///< Do nothing
1555 #define PWM_X_GENB_ACTCMPBU_INV 0x00000100 ///< Invert pwmB
1556 #define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 ///< Drive pwmB Low
1557 #define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 ///< Drive pwmB High
1558 #define PWM_X_GENB_ACTCMPAD_M 0x000000C0 ///< Action for Comparator A Down
1559 #define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 ///< Do nothing
1560 #define PWM_X_GENB_ACTCMPAD_INV 0x00000040 ///< Invert pwmB
1561 #define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 ///< Drive pwmB Low
1562 #define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 ///< Drive pwmB High
1563 #define PWM_X_GENB_ACTCMPAU_M 0x00000030 ///< Action for Comparator A Up
1564 #define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 ///< Do nothing
1565 #define PWM_X_GENB_ACTCMPAU_INV 0x00000010 ///< Invert pwmB
1566 #define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 ///< Drive pwmB Low
1567 #define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 ///< Drive pwmB High
1568 #define PWM_X_GENB_ACTLOAD_M 0x0000000C ///< Action for Counter=LOAD
1569 #define PWM_X_GENB_ACTLOAD_NONE 0x00000000 ///< Do nothing
1570 #define PWM_X_GENB_ACTLOAD_INV 0x00000004 ///< Invert pwmB
1571 #define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 ///< Drive pwmB Low
1572 #define PWM_X_GENB_ACTLOAD_ONE 0x0000000C ///< Drive pwmB High
1573 #define PWM_X_GENB_ACTZERO_M 0x00000003 ///< Action for Counter=0
1574 #define PWM_X_GENB_ACTZERO_NONE 0x00000000 ///< Do nothing
1575 #define PWM_X_GENB_ACTZERO_INV 0x00000001 ///< Invert pwmB
1576 #define PWM_X_GENB_ACTZERO_ZERO 0x00000002 ///< Drive pwmB Low
1577 #define PWM_X_GENB_ACTZERO_ONE 0x00000003 ///< Drive pwmB High
1581 * The following are defines for the bit fields in the PWM_O_X_DBCTL register.
1584 #define PWM_X_DBCTL_ENABLE 0x00000001 ///< Dead-Band Generator Enable
1588 * The following are defines for the bit fields in the PWM_O_X_DBRISE register.
1591 #define PWM_X_DBRISE_DELAY_M 0x00000FFF ///< Dead-Band Rise Delay
1592 #define PWM_X_DBRISE_DELAY_S 0
1596 * The following are defines for the bit fields in the PWM_O_X_DBFALL register.
1599 #define PWM_X_DBFALL_DELAY_M 0x00000FFF ///< Dead-Band Fall Delay
1600 #define PWM_X_DBFALL_DELAY_S 0
1604 * The following are defines for the bit fields in the QEI_O_CTL register.
1607 #define QEI_CTL_STALLEN 0x00001000 ///< Stall QEI
1608 #define QEI_CTL_INVI 0x00000800 ///< Invert Index Pulse
1609 #define QEI_CTL_INVB 0x00000400 ///< Invert PhB
1610 #define QEI_CTL_INVA 0x00000200 ///< Invert PhA
1611 #define QEI_CTL_VELDIV_M 0x000001C0 ///< Predivide Velocity
1612 #define QEI_CTL_VELDIV_1 0x00000000 ///< QEI clock /1
1613 #define QEI_CTL_VELDIV_2 0x00000040 ///< QEI clock /2
1614 #define QEI_CTL_VELDIV_4 0x00000080 ///< QEI clock /4
1615 #define QEI_CTL_VELDIV_8 0x000000C0 ///< QEI clock /8
1616 #define QEI_CTL_VELDIV_16 0x00000100 ///< QEI clock /16
1617 #define QEI_CTL_VELDIV_32 0x00000140 ///< QEI clock /32
1618 #define QEI_CTL_VELDIV_64 0x00000180 ///< QEI clock /64
1619 #define QEI_CTL_VELDIV_128 0x000001C0 ///< QEI clock /128
1620 #define QEI_CTL_VELEN 0x00000020 ///< Capture Velocity
1621 #define QEI_CTL_RESMODE 0x00000010 ///< Reset Mode
1622 #define QEI_CTL_CAPMODE 0x00000008 ///< Capture Mode
1623 #define QEI_CTL_SIGMODE 0x00000004 ///< Signal Mode
1624 #define QEI_CTL_SWAP 0x00000002 ///< Swap Signals
1625 #define QEI_CTL_ENABLE 0x00000001 ///< Enable QEI
1629 * The following are defines for the bit fields in the QEI_O_STAT register.
1632 #define QEI_STAT_DIRECTION 0x00000002 ///< Direction of Rotation
1633 #define QEI_STAT_ERROR 0x00000001 ///< Error Detected
1637 * The following are defines for the bit fields in the QEI_O_POS register.
1640 #define QEI_POS_M 0xFFFFFFFF ///< Current Position Integrator Value
1645 * The following are defines for the bit fields in the QEI_O_MAXPOS register.
1648 #define QEI_MAXPOS_M 0xFFFFFFFF ///< Maximum Position Integrator Value
1649 #define QEI_MAXPOS_S 0
1653 * The following are defines for the bit fields in the QEI_O_LOAD register.
1656 #define QEI_LOAD_M 0xFFFFFFFF ///< Velocity Timer Load Value
1657 #define QEI_LOAD_S 0
1661 * The following are defines for the bit fields in the QEI_O_TIME register.
1664 #define QEI_TIME_M 0xFFFFFFFF ///< Velocity Timer Current Value
1665 #define QEI_TIME_S 0
1669 * The following are defines for the bit fields in the QEI_O_COUNT register.
1672 #define QEI_COUNT_M 0xFFFFFFFF ///< Velocity Pulse Count
1673 #define QEI_COUNT_S 0
1677 * The following are defines for the bit fields in the QEI_O_SPEED register.
1680 #define QEI_SPEED_M 0xFFFFFFFF ///< Velocity
1681 #define QEI_SPEED_S 0
1685 * The following are defines for the bit fields in the QEI_O_INTEN register.
1688 #define QEI_INTEN_ERROR 0x00000008 ///< Phase Error Interrupt Enable
1689 #define QEI_INTEN_DIR 0x00000004 ///< Direction Change Interrupt
1691 #define QEI_INTEN_TIMER 0x00000002 ///< Timer Expires Interrupt Enable
1692 #define QEI_INTEN_INDEX 0x00000001 ///< Index Pulse Detected Interrupt
1697 * The following are defines for the bit fields in the QEI_O_RIS register.
1700 #define QEI_RIS_ERROR 0x00000008 ///< Phase Error Detected
1701 #define QEI_RIS_DIR 0x00000004 ///< Direction Change Detected
1702 #define QEI_RIS_TIMER 0x00000002 ///< Velocity Timer Expired
1703 #define QEI_RIS_INDEX 0x00000001 ///< Index Pulse Asserted
1707 * The following are defines for the bit fields in the QEI_O_ISC register.
1710 #define QEI_ISC_ERROR 0x00000008 ///< Phase Error Interrupt
1711 #define QEI_ISC_DIR 0x00000004 ///< Direction Change Interrupt
1712 #define QEI_ISC_TIMER 0x00000002 ///< Velocity Timer Expired Interrupt
1713 #define QEI_ISC_INDEX 0x00000001 ///< Index Pulse Interrupt
1717 * The following are defines for the bit fields in the TIMER_O_CFG register.
1720 #define TIMER_CFG_M 0x00000007 ///< GPTM Configuration
1721 #define TIMER_CFG_32_BIT_TIMER 0x00000000 ///< 32-bit timer configuration
1722 #define TIMER_CFG_32_BIT_RTC 0x00000001 ///< 32-bit real-time clock (RTC)
1723 ///< counter configuration
1724 #define TIMER_CFG_16_BIT 0x00000004 ///< 16-bit timer configuration. The
1725 ///< function is controlled by bits
1726 ///< 1:0 of GPTMTAMR and GPTMTBMR
1730 * The following are defines for the bit fields in the TIMER_O_TAMR register.
1733 #define TIMER_TAMR_TAAMS 0x00000008 ///< GPTM Timer A Alternate Mode
1735 #define TIMER_TAMR_TACMR 0x00000004 ///< GPTM Timer A Capture Mode
1736 #define TIMER_TAMR_TAMR_M 0x00000003 ///< GPTM Timer A Mode
1737 #define TIMER_TAMR_TAMR_1_SHOT 0x00000001 ///< One-Shot Timer mode
1738 #define TIMER_TAMR_TAMR_PERIOD 0x00000002 ///< Periodic Timer mode
1739 #define TIMER_TAMR_TAMR_CAP 0x00000003 ///< Capture mode
1743 * The following are defines for the bit fields in the TIMER_O_TBMR register.
1746 #define TIMER_TBMR_TBAMS 0x00000008 ///< GPTM Timer B Alternate Mode
1748 #define TIMER_TBMR_TBCMR 0x00000004 ///< GPTM Timer B Capture Mode
1749 #define TIMER_TBMR_TBMR_M 0x00000003 ///< GPTM Timer B Mode
1750 #define TIMER_TBMR_TBMR_1_SHOT 0x00000001 ///< One-Shot Timer mode
1751 #define TIMER_TBMR_TBMR_PERIOD 0x00000002 ///< Periodic Timer mode
1752 #define TIMER_TBMR_TBMR_CAP 0x00000003 ///< Capture mode
1756 * The following are defines for the bit fields in the TIMER_O_CTL register.
1759 #define TIMER_CTL_TBPWML 0x00004000 ///< GPTM Timer B PWM Output Level
1760 #define TIMER_CTL_TBOTE 0x00002000 ///< GPTM Timer B Output Trigger
1762 #define TIMER_CTL_TBEVENT_M 0x00000C00 ///< GPTM Timer B Event Mode
1763 #define TIMER_CTL_TBEVENT_POS 0x00000000 ///< Positive edge
1764 #define TIMER_CTL_TBEVENT_NEG 0x00000400 ///< Negative edge
1765 #define TIMER_CTL_TBEVENT_BOTH 0x00000C00 ///< Both edges
1766 #define TIMER_CTL_TBSTALL 0x00000200 ///< GPTM Timer B Stall Enable
1767 #define TIMER_CTL_TBEN 0x00000100 ///< GPTM Timer B Enable
1768 #define TIMER_CTL_TAPWML 0x00000040 ///< GPTM Timer A PWM Output Level
1769 #define TIMER_CTL_TAOTE 0x00000020 ///< GPTM Timer A Output Trigger
1771 #define TIMER_CTL_RTCEN 0x00000010 ///< GPTM RTC Enable
1772 #define TIMER_CTL_TAEVENT_M 0x0000000C ///< GPTM Timer A Event Mode
1773 #define TIMER_CTL_TAEVENT_POS 0x00000000 ///< Positive edge
1774 #define TIMER_CTL_TAEVENT_NEG 0x00000004 ///< Negative edge
1775 #define TIMER_CTL_TAEVENT_BOTH 0x0000000C ///< Both edges
1776 #define TIMER_CTL_TASTALL 0x00000002 ///< GPTM Timer A Stall Enable
1777 #define TIMER_CTL_TAEN 0x00000001 ///< GPTM Timer A Enable
1781 * The following are defines for the bit fields in the TIMER_O_IMR register.
1784 #define TIMER_IMR_CBEIM 0x00000400 ///< GPTM Capture B Event Interrupt
1786 #define TIMER_IMR_CBMIM 0x00000200 ///< GPTM Capture B Match Interrupt
1788 #define TIMER_IMR_TBTOIM 0x00000100 ///< GPTM Timer B Time-Out Interrupt
1790 #define TIMER_IMR_RTCIM 0x00000008 ///< GPTM RTC Interrupt Mask
1791 #define TIMER_IMR_CAEIM 0x00000004 ///< GPTM Capture A Event Interrupt
1793 #define TIMER_IMR_CAMIM 0x00000002 ///< GPTM Capture A Match Interrupt
1795 #define TIMER_IMR_TATOIM 0x00000001 ///< GPTM Timer A Time-Out Interrupt
1800 * The following are defines for the bit fields in the TIMER_O_RIS register.
1803 #define TIMER_RIS_CBERIS 0x00000400 ///< GPTM Capture B Event Raw
1805 #define TIMER_RIS_CBMRIS 0x00000200 ///< GPTM Capture B Match Raw
1807 #define TIMER_RIS_TBTORIS 0x00000100 ///< GPTM Timer B Time-Out Raw
1809 #define TIMER_RIS_RTCRIS 0x00000008 ///< GPTM RTC Raw Interrupt
1810 #define TIMER_RIS_CAERIS 0x00000004 ///< GPTM Capture A Event Raw
1812 #define TIMER_RIS_CAMRIS 0x00000002 ///< GPTM Capture A Match Raw
1814 #define TIMER_RIS_TATORIS 0x00000001 ///< GPTM Timer A Time-Out Raw
1819 * The following are defines for the bit fields in the TIMER_O_MIS register.
1822 #define TIMER_MIS_CBEMIS 0x00000400 ///< GPTM Capture B Event Masked
1824 #define TIMER_MIS_CBMMIS 0x00000200 ///< GPTM Capture B Match Masked
1826 #define TIMER_MIS_TBTOMIS 0x00000100 ///< GPTM Timer B Time-Out Masked
1828 #define TIMER_MIS_RTCMIS 0x00000008 ///< GPTM RTC Masked Interrupt
1829 #define TIMER_MIS_CAEMIS 0x00000004 ///< GPTM Capture A Event Masked
1831 #define TIMER_MIS_CAMMIS 0x00000002 ///< GPTM Capture A Match Masked
1833 #define TIMER_MIS_TATOMIS 0x00000001 ///< GPTM Timer A Time-Out Masked
1838 * The following are defines for the bit fields in the TIMER_O_ICR register.
1841 #define TIMER_ICR_CBECINT 0x00000400 ///< GPTM Capture B Event Interrupt
1843 #define TIMER_ICR_CBMCINT 0x00000200 ///< GPTM Capture B Match Interrupt
1845 #define TIMER_ICR_TBTOCINT 0x00000100 ///< GPTM Timer B Time-Out Interrupt
1847 #define TIMER_ICR_RTCCINT 0x00000008 ///< GPTM RTC Interrupt Clear
1848 #define TIMER_ICR_CAECINT 0x00000004 ///< GPTM Capture A Event Interrupt
1850 #define TIMER_ICR_CAMCINT 0x00000002 ///< GPTM Capture A Match Interrupt
1852 #define TIMER_ICR_TATOCINT 0x00000001 ///< GPTM Timer A Time-Out Raw
1857 * The following are defines for the bit fields in the TIMER_O_TAILR register.
1860 #define TIMER_TAILR_TAILRH_M 0xFFFF0000 ///< GPTM Timer A Interval Load
1862 #define TIMER_TAILR_TAILRL_M 0x0000FFFF ///< GPTM Timer A Interval Load
1864 #define TIMER_TAILR_TAILRH_S 16
1865 #define TIMER_TAILR_TAILRL_S 0
1869 * The following are defines for the bit fields in the TIMER_O_TBILR register.
1872 #define TIMER_TBILR_TBILRL_M 0x0000FFFF ///< GPTM Timer B Interval Load
1874 #define TIMER_TBILR_TBILRL_S 0
1878 * The following are defines for the bit fields in the TIMER_O_TAMATCHR
1882 #define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 ///< GPTM Timer A Match Register High
1883 #define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF ///< GPTM Timer A Match Register Low
1884 #define TIMER_TAMATCHR_TAMRH_S 16
1885 #define TIMER_TAMATCHR_TAMRL_S 0
1889 * The following are defines for the bit fields in the TIMER_O_TBMATCHR
1893 #define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF ///< GPTM Timer B Match Register Low
1894 #define TIMER_TBMATCHR_TBMRL_S 0
1898 * The following are defines for the bit fields in the TIMER_O_TAPR register.
1901 #define TIMER_TAPR_TAPSR_M 0x000000FF ///< GPTM Timer A Prescale
1902 #define TIMER_TAPR_TAPSR_S 0
1906 * The following are defines for the bit fields in the TIMER_O_TBPR register.
1909 #define TIMER_TBPR_TBPSR_M 0x000000FF ///< GPTM Timer B Prescale
1910 #define TIMER_TBPR_TBPSR_S 0
1914 * The following are defines for the bit fields in the TIMER_O_TAPMR register.
1917 #define TIMER_TAPMR_TAPSMR_M 0x000000FF ///< GPTM TimerA Prescale Match
1918 #define TIMER_TAPMR_TAPSMR_S 0
1922 * The following are defines for the bit fields in the TIMER_O_TBPMR register.
1925 #define TIMER_TBPMR_TBPSMR_M 0x000000FF ///< GPTM TimerB Prescale Match
1926 #define TIMER_TBPMR_TBPSMR_S 0
1930 * The following are defines for the bit fields in the TIMER_O_TAR register.
1933 #define TIMER_TAR_TARH_M 0xFFFF0000 ///< GPTM Timer A Register High
1934 #define TIMER_TAR_TARL_M 0x0000FFFF ///< GPTM Timer A Register Low
1935 #define TIMER_TAR_TARH_S 16
1936 #define TIMER_TAR_TARL_S 0
1940 * The following are defines for the bit fields in the TIMER_O_TBR register.
1943 #define TIMER_TBR_TBRL_M 0x0000FFFF ///< GPTM Timer B
1944 #define TIMER_TBR_TBRL_S 0
1948 * The following are defines for the bit fields in the ADC_O_ACTSS register.
1951 #define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable
1952 #define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable
1953 #define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable
1954 #define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable
1958 * The following are defines for the bit fields in the ADC_O_RIS register.
1961 #define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status
1962 #define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status
1963 #define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status
1964 #define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status
1968 * The following are defines for the bit fields in the ADC_O_IM register.
1971 #define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask
1972 #define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask
1973 #define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask
1974 #define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask
1978 * The following are defines for the bit fields in the ADC_O_ISC register.
1981 #define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear
1982 #define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear
1983 #define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear
1984 #define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear
1988 * The following are defines for the bit fields in the ADC_O_OSTAT register.
1991 #define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow
1992 #define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow
1993 #define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow
1994 #define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow
1998 * The following are defines for the bit fields in the ADC_O_EMUX register.
2001 #define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select
2002 #define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default)
2003 #define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0
2004 #define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1
2005 #define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2
2006 #define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4)
2007 #define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer
2008 #define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0
2009 #define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1
2010 #define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2
2011 #define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample)
2012 #define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select
2013 #define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default)
2014 #define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0
2015 #define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1
2016 #define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2
2017 #define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4)
2018 #define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer
2019 #define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0
2020 #define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1
2021 #define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2
2022 #define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample)
2023 #define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select
2024 #define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default)
2025 #define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0
2026 #define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1
2027 #define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2
2028 #define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4)
2029 #define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer
2030 #define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0
2031 #define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1
2032 #define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2
2033 #define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample)
2034 #define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select
2035 #define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default)
2036 #define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0
2037 #define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1
2038 #define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2
2039 #define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4)
2040 #define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer
2041 #define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0
2042 #define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1
2043 #define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2
2044 #define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample)
2048 * The following are defines for the bit fields in the ADC_O_USTAT register.
2051 #define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow
2052 #define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow
2053 #define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow
2054 #define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow
2058 * The following are defines for the bit fields in the ADC_O_SSPRI register.
2061 #define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority
2062 #define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority
2063 #define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority
2064 #define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority
2065 #define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority
2066 #define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority
2067 #define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority
2068 #define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority
2069 #define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority
2070 #define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority
2071 #define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority
2072 #define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority
2073 #define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority
2074 #define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority
2075 #define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority
2076 #define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority
2077 #define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority
2078 #define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority
2079 #define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority
2080 #define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority
2084 * The following are defines for the bit fields in the ADC_O_PSSI register.
2087 #define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate
2088 #define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate
2089 #define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate
2090 #define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate
2094 * The following are defines for the bit fields in the ADC_O_SAC register.
2097 #define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control
2098 #define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling
2099 #define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling
2100 #define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling
2101 #define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling
2102 #define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling
2103 #define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling
2104 #define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling
2108 * The following are defines for the bit fields in the ADC_O_SSMUX0 register.
2111 #define ADC_SSMUX0_MUX7_M 0x70000000 ///< 8th Sample Input Select
2112 #define ADC_SSMUX0_MUX6_M 0x07000000 ///< 7th Sample Input Select
2113 #define ADC_SSMUX0_MUX5_M 0x00700000 ///< 6th Sample Input Select
2114 #define ADC_SSMUX0_MUX4_M 0x00070000 ///< 5th Sample Input Select
2115 #define ADC_SSMUX0_MUX3_M 0x00007000 ///< 4th Sample Input Select
2116 #define ADC_SSMUX0_MUX2_M 0x00000700 ///< 3rd Sample Input Select
2117 #define ADC_SSMUX0_MUX1_M 0x00000070 ///< 2nd Sample Input Select
2118 #define ADC_SSMUX0_MUX0_M 0x00000007 ///< 1st Sample Input Select
2119 #define ADC_SSMUX0_MUX7_S 28
2120 #define ADC_SSMUX0_MUX6_S 24
2121 #define ADC_SSMUX0_MUX5_S 20
2122 #define ADC_SSMUX0_MUX4_S 16
2123 #define ADC_SSMUX0_MUX3_S 12
2124 #define ADC_SSMUX0_MUX2_S 8
2125 #define ADC_SSMUX0_MUX1_S 4
2126 #define ADC_SSMUX0_MUX0_S 0
2130 * The following are defines for the bit fields in the ADC_O_SSCTL0 register.
2133 #define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select
2134 #define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable
2135 #define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence
2136 #define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select
2137 #define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select
2138 #define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable
2139 #define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence
2140 #define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select
2141 #define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select
2142 #define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable
2143 #define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence
2144 #define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select
2145 #define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select
2146 #define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable
2147 #define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence
2148 #define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select
2149 #define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
2150 #define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable
2151 #define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence
2152 #define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select
2153 #define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
2154 #define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
2155 #define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence
2156 #define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select
2157 #define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
2158 #define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
2159 #define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence
2160 #define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select
2161 #define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
2162 #define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable
2163 #define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence
2164 #define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select
2168 * The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
2171 #define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data
2172 #define ADC_SSFIFO0_DATA_S 0
2176 * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
2179 #define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full
2180 #define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty
2181 #define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer
2182 #define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer
2183 #define ADC_SSFSTAT0_HPTR_S 4
2184 #define ADC_SSFSTAT0_TPTR_S 0
2188 * The following are defines for the bit fields in the ADC_O_SSMUX1 register.
2191 #define ADC_SSMUX1_MUX3_M 0x00007000 ///< 4th Sample Input Select
2192 #define ADC_SSMUX1_MUX2_M 0x00000700 ///< 3rd Sample Input Select
2193 #define ADC_SSMUX1_MUX1_M 0x00000070 ///< 2nd Sample Input Select
2194 #define ADC_SSMUX1_MUX0_M 0x00000007 ///< 1st Sample Input Select
2195 #define ADC_SSMUX1_MUX3_S 12
2196 #define ADC_SSMUX1_MUX2_S 8
2197 #define ADC_SSMUX1_MUX1_S 4
2198 #define ADC_SSMUX1_MUX0_S 0
2202 * The following are defines for the bit fields in the ADC_O_SSCTL1 register.
2205 #define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
2206 #define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable
2207 #define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence
2208 #define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select
2209 #define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
2210 #define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
2211 #define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence
2212 #define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select
2213 #define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
2214 #define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
2215 #define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence
2216 #define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select
2217 #define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
2218 #define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable
2219 #define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence
2220 #define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select
2224 * The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
2227 #define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data
2228 #define ADC_SSFIFO1_DATA_S 0
2232 * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
2235 #define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full
2236 #define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty
2237 #define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer
2238 #define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer
2239 #define ADC_SSFSTAT1_HPTR_S 4
2240 #define ADC_SSFSTAT1_TPTR_S 0
2244 * The following are defines for the bit fields in the ADC_O_SSMUX2 register.
2247 #define ADC_SSMUX2_MUX3_M 0x00007000 ///< 4th Sample Input Select
2248 #define ADC_SSMUX2_MUX2_M 0x00000700 ///< 3rd Sample Input Select
2249 #define ADC_SSMUX2_MUX1_M 0x00000070 ///< 2nd Sample Input Select
2250 #define ADC_SSMUX2_MUX0_M 0x00000007 ///< 1st Sample Input Select
2251 #define ADC_SSMUX2_MUX3_S 12
2252 #define ADC_SSMUX2_MUX2_S 8
2253 #define ADC_SSMUX2_MUX1_S 4
2254 #define ADC_SSMUX2_MUX0_S 0
2258 * The following are defines for the bit fields in the ADC_O_SSCTL2 register.
2261 #define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
2262 #define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable
2263 #define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence
2264 #define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select
2265 #define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
2266 #define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
2267 #define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence
2268 #define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select
2269 #define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
2270 #define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
2271 #define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence
2272 #define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select
2273 #define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
2274 #define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable
2275 #define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence
2276 #define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select
2280 * The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
2283 #define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data
2284 #define ADC_SSFIFO2_DATA_S 0
2288 * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
2291 #define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full
2292 #define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty
2293 #define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer
2294 #define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer
2295 #define ADC_SSFSTAT2_HPTR_S 4
2296 #define ADC_SSFSTAT2_TPTR_S 0
2300 * The following are defines for the bit fields in the ADC_O_SSMUX3 register.
2303 #define ADC_SSMUX3_MUX0_M 0x00000007 ///< 1st Sample Input Select
2304 #define ADC_SSMUX3_MUX0_S 0
2308 * The following are defines for the bit fields in the ADC_O_SSCTL3 register.
2311 #define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
2312 #define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable
2313 #define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence
2314 #define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select
2318 * The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
2321 #define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data
2322 #define ADC_SSFIFO3_DATA_S 0
2326 * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
2329 #define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full
2330 #define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty
2331 #define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer
2332 #define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer
2333 #define ADC_SSFSTAT3_HPTR_S 4
2334 #define ADC_SSFSTAT3_TPTR_S 0
2338 * The following are defines for the bit fields in the ADC_O_TMLB register.
2341 #define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable
2345 * The following are defines for the the interpretation of the data in the
2346 * SSFIFOx when the ADC TMLB is enabled.
2349 #define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
2350 #define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
2351 #define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
2352 #define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
2353 #define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
2354 #define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift
2355 #define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift
2359 * The following are defines for the bit fields in the COMP_O_ACMIS register.
2362 #define COMP_ACMIS_IN2 0x00000004 ///< Comparator 2 Masked Interrupt
2364 #define COMP_ACMIS_IN1 0x00000002 ///< Comparator 1 Masked Interrupt
2366 #define COMP_ACMIS_IN0 0x00000001 ///< Comparator 0 Masked Interrupt
2371 * The following are defines for the bit fields in the COMP_O_ACRIS register.
2374 #define COMP_ACRIS_IN2 0x00000004 ///< Comparator 2 Interrupt Status
2375 #define COMP_ACRIS_IN1 0x00000002 ///< Comparator 1 Interrupt Status
2376 #define COMP_ACRIS_IN0 0x00000001 ///< Comparator 0 Interrupt Status
2380 * The following are defines for the bit fields in the COMP_O_ACINTEN register.
2383 #define COMP_ACINTEN_IN2 0x00000004 ///< Comparator 2 Interrupt Enable
2384 #define COMP_ACINTEN_IN1 0x00000002 ///< Comparator 1 Interrupt Enable
2385 #define COMP_ACINTEN_IN0 0x00000001 ///< Comparator 0 Interrupt Enable
2389 * The following are defines for the bit fields in the COMP_O_ACREFCTL
2393 #define COMP_ACREFCTL_EN 0x00000200 ///< Resistor Ladder Enable
2394 #define COMP_ACREFCTL_RNG 0x00000100 ///< Resistor Ladder Range
2395 #define COMP_ACREFCTL_VREF_M 0x0000000F ///< Resistor Ladder Voltage Ref
2396 #define COMP_ACREFCTL_VREF_S 0
2400 * The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
2403 #define COMP_ACSTAT0_OVAL 0x00000002 ///< Comparator Output Value
2407 * The following are defines for the bit fields in the COMP_O_ACCTL0 register.
2410 #define COMP_ACCTL0_TOEN 0x00000800 ///< Trigger Output Enable
2411 #define COMP_ACCTL0_ASRCP_M 0x00000600 ///< Analog Source Positive
2412 #define COMP_ACCTL0_ASRCP_PIN 0x00000000 ///< Pin value of Cn+
2413 #define COMP_ACCTL0_ASRCP_PIN0 0x00000200 ///< Pin value of C0+
2414 #define COMP_ACCTL0_ASRCP_REF 0x00000400 ///< Internal voltage reference
2416 #define COMP_ACCTL0_TSLVAL 0x00000080 ///< Trigger Sense Level Value
2417 #define COMP_ACCTL0_TSEN_M 0x00000060 ///< Trigger Sense
2418 #define COMP_ACCTL0_TSEN_LEVEL 0x00000000 ///< Level sense, see TSLVAL
2419 #define COMP_ACCTL0_TSEN_FALL 0x00000020 ///< Falling edge
2420 #define COMP_ACCTL0_TSEN_RISE 0x00000040 ///< Rising edge
2421 #define COMP_ACCTL0_TSEN_BOTH 0x00000060 ///< Either edge
2422 #define COMP_ACCTL0_ISLVAL 0x00000010 ///< Interrupt Sense Level Value
2423 #define COMP_ACCTL0_ISEN_M 0x0000000C ///< Interrupt Sense
2424 #define COMP_ACCTL0_ISEN_LEVEL 0x00000000 ///< Level sense, see ISLVAL
2425 #define COMP_ACCTL0_ISEN_FALL 0x00000004 ///< Falling edge
2426 #define COMP_ACCTL0_ISEN_RISE 0x00000008 ///< Rising edge
2427 #define COMP_ACCTL0_ISEN_BOTH 0x0000000C ///< Either edge
2428 #define COMP_ACCTL0_CINV 0x00000002 ///< Comparator Output Invert
2432 * The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
2435 #define COMP_ACSTAT1_OVAL 0x00000002 ///< Comparator Output Value
2439 * The following are defines for the bit fields in the COMP_O_ACCTL1 register.
2442 #define COMP_ACCTL1_TOEN 0x00000800 ///< Trigger Output Enable
2443 #define COMP_ACCTL1_ASRCP_M 0x00000600 ///< Analog Source Positive
2444 #define COMP_ACCTL1_ASRCP_PIN 0x00000000 ///< Pin value of Cn+
2445 #define COMP_ACCTL1_ASRCP_PIN0 0x00000200 ///< Pin value of C0+
2446 #define COMP_ACCTL1_ASRCP_REF 0x00000400 ///< Internal voltage reference
2448 #define COMP_ACCTL1_TSLVAL 0x00000080 ///< Trigger Sense Level Value
2449 #define COMP_ACCTL1_TSEN_M 0x00000060 ///< Trigger Sense
2450 #define COMP_ACCTL1_TSEN_LEVEL 0x00000000 ///< Level sense, see TSLVAL
2451 #define COMP_ACCTL1_TSEN_FALL 0x00000020 ///< Falling edge
2452 #define COMP_ACCTL1_TSEN_RISE 0x00000040 ///< Rising edge
2453 #define COMP_ACCTL1_TSEN_BOTH 0x00000060 ///< Either edge
2454 #define COMP_ACCTL1_ISLVAL 0x00000010 ///< Interrupt Sense Level Value
2455 #define COMP_ACCTL1_ISEN_M 0x0000000C ///< Interrupt Sense
2456 #define COMP_ACCTL1_ISEN_LEVEL 0x00000000 ///< Level sense, see ISLVAL
2457 #define COMP_ACCTL1_ISEN_FALL 0x00000004 ///< Falling edge
2458 #define COMP_ACCTL1_ISEN_RISE 0x00000008 ///< Rising edge
2459 #define COMP_ACCTL1_ISEN_BOTH 0x0000000C ///< Either edge
2460 #define COMP_ACCTL1_CINV 0x00000002 ///< Comparator Output Invert
2464 * The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
2467 #define COMP_ACSTAT2_OVAL 0x00000002 ///< Comparator Output Value
2471 * The following are defines for the bit fields in the COMP_O_ACCTL2 register.
2474 #define COMP_ACCTL2_TOEN 0x00000800 ///< Trigger Output Enable
2475 #define COMP_ACCTL2_ASRCP_M 0x00000600 ///< Analog Source Positive
2476 #define COMP_ACCTL2_ASRCP_PIN 0x00000000 ///< Pin value of Cn+
2477 #define COMP_ACCTL2_ASRCP_PIN0 0x00000200 ///< Pin value of C0+
2478 #define COMP_ACCTL2_ASRCP_REF 0x00000400 ///< Internal voltage reference
2480 #define COMP_ACCTL2_TSLVAL 0x00000080 ///< Trigger Sense Level Value
2481 #define COMP_ACCTL2_TSEN_M 0x00000060 ///< Trigger Sense
2482 #define COMP_ACCTL2_TSEN_LEVEL 0x00000000 ///< Level sense, see TSLVAL
2483 #define COMP_ACCTL2_TSEN_FALL 0x00000020 ///< Falling edge
2484 #define COMP_ACCTL2_TSEN_RISE 0x00000040 ///< Rising edge
2485 #define COMP_ACCTL2_TSEN_BOTH 0x00000060 ///< Either edge
2486 #define COMP_ACCTL2_ISLVAL 0x00000010 ///< Interrupt Sense Level Value
2487 #define COMP_ACCTL2_ISEN_M 0x0000000C ///< Interrupt Sense
2488 #define COMP_ACCTL2_ISEN_LEVEL 0x00000000 ///< Level sense, see ISLVAL
2489 #define COMP_ACCTL2_ISEN_FALL 0x00000004 ///< Falling edge
2490 #define COMP_ACCTL2_ISEN_RISE 0x00000008 ///< Rising edge
2491 #define COMP_ACCTL2_ISEN_BOTH 0x0000000C ///< Either edge
2492 #define COMP_ACCTL2_CINV 0x00000002 ///< Comparator Output Invert
2496 * The following are defines for the bit fields in the HIB_RTCC register.
2499 #define HIB_RTCC_M 0xFFFFFFFF ///< RTC Counter
2500 #define HIB_RTCC_S 0
2504 * The following are defines for the bit fields in the HIB_RTCM0 register.
2507 #define HIB_RTCM0_M 0xFFFFFFFF ///< RTC Match 0
2508 #define HIB_RTCM0_S 0
2512 * The following are defines for the bit fields in the HIB_RTCM1 register.
2515 #define HIB_RTCM1_M 0xFFFFFFFF ///< RTC Match 1
2516 #define HIB_RTCM1_S 0
2520 * The following are defines for the bit fields in the HIB_RTCLD register.
2523 #define HIB_RTCLD_M 0xFFFFFFFF ///< RTC Load
2524 #define HIB_RTCLD_S 0
2528 * The following are defines for the bit fields in the HIB_CTL register.
2531 #define HIB_CTL_VABORT 0x00000080 ///< Power Cut Abort Enable
2532 #define HIB_CTL_CLK32EN 0x00000040 ///< Clocking Enable
2533 #define HIB_CTL_LOWBATEN 0x00000020 ///< Low Battery Monitoring Enable
2534 #define HIB_CTL_PINWEN 0x00000010 ///< External WAKE Pin Enable
2535 #define HIB_CTL_RTCWEN 0x00000008 ///< RTC Wake-up Enable
2536 #define HIB_CTL_CLKSEL 0x00000004 ///< Hibernation Module Clock Select
2537 #define HIB_CTL_HIBREQ 0x00000002 ///< Hibernation Request
2538 #define HIB_CTL_RTCEN 0x00000001 ///< RTC Timer Enable
2542 * The following are defines for the bit fields in the HIB_IM register.
2545 #define HIB_IM_EXTW 0x00000008 ///< External Wake-Up Interrupt Mask
2546 #define HIB_IM_LOWBAT 0x00000004 ///< Low Battery Voltage Interrupt
2548 #define HIB_IM_RTCALT1 0x00000002 ///< RTC Alert 1 Interrupt Mask
2549 #define HIB_IM_RTCALT0 0x00000001 ///< RTC Alert 0 Interrupt Mask
2553 * The following are defines for the bit fields in the HIB_RIS register.
2556 #define HIB_RIS_EXTW 0x00000008 ///< External Wake-Up Raw Interrupt
2558 #define HIB_RIS_LOWBAT 0x00000004 ///< Low Battery Voltage Raw
2559 ///< Interrupt Status
2560 #define HIB_RIS_RTCALT1 0x00000002 ///< RTC Alert 1 Raw Interrupt Status
2561 #define HIB_RIS_RTCALT0 0x00000001 ///< RTC Alert 0 Raw Interrupt Status
2565 * The following are defines for the bit fields in the HIB_MIS register.
2568 #define HIB_MIS_EXTW 0x00000008 ///< External Wake-Up Masked
2569 ///< Interrupt Status
2570 #define HIB_MIS_LOWBAT 0x00000004 ///< Low Battery Voltage Masked
2571 ///< Interrupt Status
2572 #define HIB_MIS_RTCALT1 0x00000002 ///< RTC Alert 1 Masked Interrupt
2574 #define HIB_MIS_RTCALT0 0x00000001 ///< RTC Alert 0 Masked Interrupt
2579 * The following are defines for the bit fields in the HIB_IC register.
2582 #define HIB_IC_EXTW 0x00000008 ///< External Wake-Up Masked
2583 ///< Interrupt Clear
2584 #define HIB_IC_LOWBAT 0x00000004 ///< Low Battery Voltage Masked
2585 ///< Interrupt Clear
2586 #define HIB_IC_RTCALT1 0x00000002 ///< RTC Alert1 Masked Interrupt
2588 #define HIB_IC_RTCALT0 0x00000001 ///< RTC Alert0 Masked Interrupt
2593 * The following are defines for the bit fields in the HIB_RTCT register.
2596 #define HIB_RTCT_TRIM_M 0x0000FFFF ///< RTC Trim Value
2597 #define HIB_RTCT_TRIM_S 0
2601 * The following are defines for the bit fields in the HIB_DATA register.
2604 #define HIB_DATA_RTD_M 0xFFFFFFFF ///< Hibernation Module NV Data
2605 #define HIB_DATA_RTD_S 0
2609 * The following are defines for the bit fields in the FLASH_FMA register.
2612 #define FLASH_FMA_OFFSET_M 0x0003FFFF ///< Address Offset
2613 #define FLASH_FMA_OFFSET_S 0
2617 * The following are defines for the bit fields in the FLASH_FMD register.
2620 #define FLASH_FMD_DATA_M 0xFFFFFFFF ///< Data Value
2621 #define FLASH_FMD_DATA_S 0
2625 * The following are defines for the bit fields in the FLASH_FMC register.
2628 #define FLASH_FMC_WRKEY 0xA4420000 ///< FLASH write key
2629 #define FLASH_FMC_COMT 0x00000008 ///< Commit Register Value
2630 #define FLASH_FMC_MERASE 0x00000004 ///< Mass Erase Flash Memory
2631 #define FLASH_FMC_ERASE 0x00000002 ///< Erase a Page of Flash Memory
2632 #define FLASH_FMC_WRITE 0x00000001 ///< Write a Word into Flash Memory
2636 * The following are defines for the bit fields in the FLASH_FCRIS register.
2639 #define FLASH_FCRIS_PRIS 0x00000002 ///< Programming Raw Interrupt Status
2640 #define FLASH_FCRIS_ARIS 0x00000001 ///< Access Raw Interrupt Status
2644 * The following are defines for the bit fields in the FLASH_FCIM register.
2647 #define FLASH_FCIM_PMASK 0x00000002 ///< Programming Interrupt Mask
2648 #define FLASH_FCIM_AMASK 0x00000001 ///< Access Interrupt Mask
2652 * The following are defines for the bit fields in the FLASH_FCMISC register.
2655 #define FLASH_FCMISC_PMISC 0x00000002 ///< Programming Masked Interrupt
2656 ///< Status and Clear
2657 #define FLASH_FCMISC_AMISC 0x00000001 ///< Access Masked Interrupt Status
2662 * The following are defines for the bit fields in the FLASH_USECRL register.
2665 #define FLASH_USECRL_M 0x000000FF ///< Microsecond Reload Value
2666 #define FLASH_USECRL_S 0
2670 * The following are defines for the bit fields in the FLASH_USERDBG register.
2673 #define FLASH_USERDBG_NW 0x80000000 ///< User Debug Not Written
2674 #define FLASH_USERDBG_DATA_M 0x7FFFFFFC ///< User Data
2675 #define FLASH_USERDBG_DBG1 0x00000002 ///< Debug Control 1
2676 #define FLASH_USERDBG_DBG0 0x00000001 ///< Debug Control 0
2677 #define FLASH_USERDBG_DATA_S 2
2681 * The following are defines for the bit fields in the FLASH_USERREG0 register.
2684 #define FLASH_USERREG0_NW 0x80000000 ///< Not Written
2685 #define FLASH_USERREG0_DATA_M 0x7FFFFFFF ///< User Data
2686 #define FLASH_USERREG0_DATA_S 0
2690 * The following are defines for the bit fields in the FLASH_USERREG1 register.
2693 #define FLASH_USERREG1_NW 0x80000000 ///< Not Written
2694 #define FLASH_USERREG1_DATA_M 0x7FFFFFFF ///< User Data
2695 #define FLASH_USERREG1_DATA_S 0
2699 * The following are defines for the erase size of the FLASH block that is
2700 * erased by an erase operation, and the protect size is the size of the FLASH
2701 * block that is protected by each protection register.
2704 #define FLASH_PROTECT_SIZE 0x00000800
2705 #define FLASH_ERASE_SIZE 0x00000400
2709 * The following are defines for the bit fields in the NVIC_INT_TYPE register.
2712 #define NVIC_INT_TYPE_LINES_M 0x0000001F ///< Number of interrupt lines (x32)
2713 #define NVIC_INT_TYPE_LINES_S 0
2717 * The following are defines for the bit fields in the NVIC_ST_CTRL register.
2720 #define NVIC_ST_CTRL_COUNT 0x00010000 ///< Count flag
2721 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 ///< Clock Source
2722 #define NVIC_ST_CTRL_INTEN 0x00000002 ///< Interrupt enable
2723 #define NVIC_ST_CTRL_ENABLE 0x00000001 ///< Counter mode
2727 * The following are defines for the bit fields in the NVIC_ST_RELOAD register.
2730 #define NVIC_ST_RELOAD_M 0x00FFFFFF ///< Counter load value
2731 #define NVIC_ST_RELOAD_S 0
2735 * The following are defines for the bit fields in the NVIC_ST_CURRENT
2739 #define NVIC_ST_CURRENT_M 0x00FFFFFF ///< Counter current value
2740 #define NVIC_ST_CURRENT_S 0
2744 * The following are defines for the bit fields in the NVIC_ST_CAL register.
2747 #define NVIC_ST_CAL_NOREF 0x80000000 ///< No reference clock
2748 #define NVIC_ST_CAL_SKEW 0x40000000 ///< Clock skew
2749 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF ///< 1ms reference value
2750 #define NVIC_ST_CAL_ONEMS_S 0
2754 * The following are defines for the bit fields in the NVIC_EN0 register.
2757 #define NVIC_EN0_INT31 0x80000000 ///< Interrupt 31 enable
2758 #define NVIC_EN0_INT30 0x40000000 ///< Interrupt 30 enable
2759 #define NVIC_EN0_INT29 0x20000000 ///< Interrupt 29 enable
2760 #define NVIC_EN0_INT28 0x10000000 ///< Interrupt 28 enable
2761 #define NVIC_EN0_INT27 0x08000000 ///< Interrupt 27 enable
2762 #define NVIC_EN0_INT26 0x04000000 ///< Interrupt 26 enable
2763 #define NVIC_EN0_INT25 0x02000000 ///< Interrupt 25 enable
2764 #define NVIC_EN0_INT24 0x01000000 ///< Interrupt 24 enable
2765 #define NVIC_EN0_INT23 0x00800000 ///< Interrupt 23 enable
2766 #define NVIC_EN0_INT22 0x00400000 ///< Interrupt 22 enable
2767 #define NVIC_EN0_INT21 0x00200000 ///< Interrupt 21 enable
2768 #define NVIC_EN0_INT20 0x00100000 ///< Interrupt 20 enable
2769 #define NVIC_EN0_INT19 0x00080000 ///< Interrupt 19 enable
2770 #define NVIC_EN0_INT18 0x00040000 ///< Interrupt 18 enable
2771 #define NVIC_EN0_INT17 0x00020000 ///< Interrupt 17 enable
2772 #define NVIC_EN0_INT16 0x00010000 ///< Interrupt 16 enable
2773 #define NVIC_EN0_INT15 0x00008000 ///< Interrupt 15 enable
2774 #define NVIC_EN0_INT14 0x00004000 ///< Interrupt 14 enable
2775 #define NVIC_EN0_INT13 0x00002000 ///< Interrupt 13 enable
2776 #define NVIC_EN0_INT12 0x00001000 ///< Interrupt 12 enable
2777 #define NVIC_EN0_INT11 0x00000800 ///< Interrupt 11 enable
2778 #define NVIC_EN0_INT10 0x00000400 ///< Interrupt 10 enable
2779 #define NVIC_EN0_INT9 0x00000200 ///< Interrupt 9 enable
2780 #define NVIC_EN0_INT8 0x00000100 ///< Interrupt 8 enable
2781 #define NVIC_EN0_INT7 0x00000080 ///< Interrupt 7 enable
2782 #define NVIC_EN0_INT6 0x00000040 ///< Interrupt 6 enable
2783 #define NVIC_EN0_INT5 0x00000020 ///< Interrupt 5 enable
2784 #define NVIC_EN0_INT4 0x00000010 ///< Interrupt 4 enable
2785 #define NVIC_EN0_INT3 0x00000008 ///< Interrupt 3 enable
2786 #define NVIC_EN0_INT2 0x00000004 ///< Interrupt 2 enable
2787 #define NVIC_EN0_INT1 0x00000002 ///< Interrupt 1 enable
2788 #define NVIC_EN0_INT0 0x00000001 ///< Interrupt 0 enable
2792 * The following are defines for the bit fields in the NVIC_EN1 register.
2795 #define NVIC_EN1_INT59 0x08000000 ///< Interrupt 59 enable
2796 #define NVIC_EN1_INT58 0x04000000 ///< Interrupt 58 enable
2797 #define NVIC_EN1_INT57 0x02000000 ///< Interrupt 57 enable
2798 #define NVIC_EN1_INT56 0x01000000 ///< Interrupt 56 enable
2799 #define NVIC_EN1_INT55 0x00800000 ///< Interrupt 55 enable
2800 #define NVIC_EN1_INT54 0x00400000 ///< Interrupt 54 enable
2801 #define NVIC_EN1_INT53 0x00200000 ///< Interrupt 53 enable
2802 #define NVIC_EN1_INT52 0x00100000 ///< Interrupt 52 enable
2803 #define NVIC_EN1_INT51 0x00080000 ///< Interrupt 51 enable
2804 #define NVIC_EN1_INT50 0x00040000 ///< Interrupt 50 enable
2805 #define NVIC_EN1_INT49 0x00020000 ///< Interrupt 49 enable
2806 #define NVIC_EN1_INT48 0x00010000 ///< Interrupt 48 enable
2807 #define NVIC_EN1_INT47 0x00008000 ///< Interrupt 47 enable
2808 #define NVIC_EN1_INT46 0x00004000 ///< Interrupt 46 enable
2809 #define NVIC_EN1_INT45 0x00002000 ///< Interrupt 45 enable
2810 #define NVIC_EN1_INT44 0x00001000 ///< Interrupt 44 enable
2811 #define NVIC_EN1_INT43 0x00000800 ///< Interrupt 43 enable
2812 #define NVIC_EN1_INT42 0x00000400 ///< Interrupt 42 enable
2813 #define NVIC_EN1_INT41 0x00000200 ///< Interrupt 41 enable
2814 #define NVIC_EN1_INT40 0x00000100 ///< Interrupt 40 enable
2815 #define NVIC_EN1_INT39 0x00000080 ///< Interrupt 39 enable
2816 #define NVIC_EN1_INT38 0x00000040 ///< Interrupt 38 enable
2817 #define NVIC_EN1_INT37 0x00000020 ///< Interrupt 37 enable
2818 #define NVIC_EN1_INT36 0x00000010 ///< Interrupt 36 enable
2819 #define NVIC_EN1_INT35 0x00000008 ///< Interrupt 35 enable
2820 #define NVIC_EN1_INT34 0x00000004 ///< Interrupt 34 enable
2821 #define NVIC_EN1_INT33 0x00000002 ///< Interrupt 33 enable
2822 #define NVIC_EN1_INT32 0x00000001 ///< Interrupt 32 enable
2826 * The following are defines for the bit fields in the NVIC_DIS0 register.
2829 #define NVIC_DIS0_INT31 0x80000000 ///< Interrupt 31 disable
2830 #define NVIC_DIS0_INT30 0x40000000 ///< Interrupt 30 disable
2831 #define NVIC_DIS0_INT29 0x20000000 ///< Interrupt 29 disable
2832 #define NVIC_DIS0_INT28 0x10000000 ///< Interrupt 28 disable
2833 #define NVIC_DIS0_INT27 0x08000000 ///< Interrupt 27 disable
2834 #define NVIC_DIS0_INT26 0x04000000 ///< Interrupt 26 disable
2835 #define NVIC_DIS0_INT25 0x02000000 ///< Interrupt 25 disable
2836 #define NVIC_DIS0_INT24 0x01000000 ///< Interrupt 24 disable
2837 #define NVIC_DIS0_INT23 0x00800000 ///< Interrupt 23 disable
2838 #define NVIC_DIS0_INT22 0x00400000 ///< Interrupt 22 disable
2839 #define NVIC_DIS0_INT21 0x00200000 ///< Interrupt 21 disable
2840 #define NVIC_DIS0_INT20 0x00100000 ///< Interrupt 20 disable
2841 #define NVIC_DIS0_INT19 0x00080000 ///< Interrupt 19 disable
2842 #define NVIC_DIS0_INT18 0x00040000 ///< Interrupt 18 disable
2843 #define NVIC_DIS0_INT17 0x00020000 ///< Interrupt 17 disable
2844 #define NVIC_DIS0_INT16 0x00010000 ///< Interrupt 16 disable
2845 #define NVIC_DIS0_INT15 0x00008000 ///< Interrupt 15 disable
2846 #define NVIC_DIS0_INT14 0x00004000 ///< Interrupt 14 disable
2847 #define NVIC_DIS0_INT13 0x00002000 ///< Interrupt 13 disable
2848 #define NVIC_DIS0_INT12 0x00001000 ///< Interrupt 12 disable
2849 #define NVIC_DIS0_INT11 0x00000800 ///< Interrupt 11 disable
2850 #define NVIC_DIS0_INT10 0x00000400 ///< Interrupt 10 disable
2851 #define NVIC_DIS0_INT9 0x00000200 ///< Interrupt 9 disable
2852 #define NVIC_DIS0_INT8 0x00000100 ///< Interrupt 8 disable
2853 #define NVIC_DIS0_INT7 0x00000080 ///< Interrupt 7 disable
2854 #define NVIC_DIS0_INT6 0x00000040 ///< Interrupt 6 disable
2855 #define NVIC_DIS0_INT5 0x00000020 ///< Interrupt 5 disable
2856 #define NVIC_DIS0_INT4 0x00000010 ///< Interrupt 4 disable
2857 #define NVIC_DIS0_INT3 0x00000008 ///< Interrupt 3 disable
2858 #define NVIC_DIS0_INT2 0x00000004 ///< Interrupt 2 disable
2859 #define NVIC_DIS0_INT1 0x00000002 ///< Interrupt 1 disable
2860 #define NVIC_DIS0_INT0 0x00000001 ///< Interrupt 0 disable
2864 * The following are defines for the bit fields in the NVIC_DIS1 register.
2867 #define NVIC_DIS1_INT59 0x08000000 ///< Interrupt 59 disable
2868 #define NVIC_DIS1_INT58 0x04000000 ///< Interrupt 58 disable
2869 #define NVIC_DIS1_INT57 0x02000000 ///< Interrupt 57 disable
2870 #define NVIC_DIS1_INT56 0x01000000 ///< Interrupt 56 disable
2871 #define NVIC_DIS1_INT55 0x00800000 ///< Interrupt 55 disable
2872 #define NVIC_DIS1_INT54 0x00400000 ///< Interrupt 54 disable
2873 #define NVIC_DIS1_INT53 0x00200000 ///< Interrupt 53 disable
2874 #define NVIC_DIS1_INT52 0x00100000 ///< Interrupt 52 disable
2875 #define NVIC_DIS1_INT51 0x00080000 ///< Interrupt 51 disable
2876 #define NVIC_DIS1_INT50 0x00040000 ///< Interrupt 50 disable
2877 #define NVIC_DIS1_INT49 0x00020000 ///< Interrupt 49 disable
2878 #define NVIC_DIS1_INT48 0x00010000 ///< Interrupt 48 disable
2879 #define NVIC_DIS1_INT47 0x00008000 ///< Interrupt 47 disable
2880 #define NVIC_DIS1_INT46 0x00004000 ///< Interrupt 46 disable
2881 #define NVIC_DIS1_INT45 0x00002000 ///< Interrupt 45 disable
2882 #define NVIC_DIS1_INT44 0x00001000 ///< Interrupt 44 disable
2883 #define NVIC_DIS1_INT43 0x00000800 ///< Interrupt 43 disable
2884 #define NVIC_DIS1_INT42 0x00000400 ///< Interrupt 42 disable
2885 #define NVIC_DIS1_INT41 0x00000200 ///< Interrupt 41 disable
2886 #define NVIC_DIS1_INT40 0x00000100 ///< Interrupt 40 disable
2887 #define NVIC_DIS1_INT39 0x00000080 ///< Interrupt 39 disable
2888 #define NVIC_DIS1_INT38 0x00000040 ///< Interrupt 38 disable
2889 #define NVIC_DIS1_INT37 0x00000020 ///< Interrupt 37 disable
2890 #define NVIC_DIS1_INT36 0x00000010 ///< Interrupt 36 disable
2891 #define NVIC_DIS1_INT35 0x00000008 ///< Interrupt 35 disable
2892 #define NVIC_DIS1_INT34 0x00000004 ///< Interrupt 34 disable
2893 #define NVIC_DIS1_INT33 0x00000002 ///< Interrupt 33 disable
2894 #define NVIC_DIS1_INT32 0x00000001 ///< Interrupt 32 disable
2898 * The following are defines for the bit fields in the NVIC_PEND0 register.
2901 #define NVIC_PEND0_INT31 0x80000000 ///< Interrupt 31 pend
2902 #define NVIC_PEND0_INT30 0x40000000 ///< Interrupt 30 pend
2903 #define NVIC_PEND0_INT29 0x20000000 ///< Interrupt 29 pend
2904 #define NVIC_PEND0_INT28 0x10000000 ///< Interrupt 28 pend
2905 #define NVIC_PEND0_INT27 0x08000000 ///< Interrupt 27 pend
2906 #define NVIC_PEND0_INT26 0x04000000 ///< Interrupt 26 pend
2907 #define NVIC_PEND0_INT25 0x02000000 ///< Interrupt 25 pend
2908 #define NVIC_PEND0_INT24 0x01000000 ///< Interrupt 24 pend
2909 #define NVIC_PEND0_INT23 0x00800000 ///< Interrupt 23 pend
2910 #define NVIC_PEND0_INT22 0x00400000 ///< Interrupt 22 pend
2911 #define NVIC_PEND0_INT21 0x00200000 ///< Interrupt 21 pend
2912 #define NVIC_PEND0_INT20 0x00100000 ///< Interrupt 20 pend
2913 #define NVIC_PEND0_INT19 0x00080000 ///< Interrupt 19 pend
2914 #define NVIC_PEND0_INT18 0x00040000 ///< Interrupt 18 pend
2915 #define NVIC_PEND0_INT17 0x00020000 ///< Interrupt 17 pend
2916 #define NVIC_PEND0_INT16 0x00010000 ///< Interrupt 16 pend
2917 #define NVIC_PEND0_INT15 0x00008000 ///< Interrupt 15 pend
2918 #define NVIC_PEND0_INT14 0x00004000 ///< Interrupt 14 pend
2919 #define NVIC_PEND0_INT13 0x00002000 ///< Interrupt 13 pend
2920 #define NVIC_PEND0_INT12 0x00001000 ///< Interrupt 12 pend
2921 #define NVIC_PEND0_INT11 0x00000800 ///< Interrupt 11 pend
2922 #define NVIC_PEND0_INT10 0x00000400 ///< Interrupt 10 pend
2923 #define NVIC_PEND0_INT9 0x00000200 ///< Interrupt 9 pend
2924 #define NVIC_PEND0_INT8 0x00000100 ///< Interrupt 8 pend
2925 #define NVIC_PEND0_INT7 0x00000080 ///< Interrupt 7 pend
2926 #define NVIC_PEND0_INT6 0x00000040 ///< Interrupt 6 pend
2927 #define NVIC_PEND0_INT5 0x00000020 ///< Interrupt 5 pend
2928 #define NVIC_PEND0_INT4 0x00000010 ///< Interrupt 4 pend
2929 #define NVIC_PEND0_INT3 0x00000008 ///< Interrupt 3 pend
2930 #define NVIC_PEND0_INT2 0x00000004 ///< Interrupt 2 pend
2931 #define NVIC_PEND0_INT1 0x00000002 ///< Interrupt 1 pend
2932 #define NVIC_PEND0_INT0 0x00000001 ///< Interrupt 0 pend
2936 * The following are defines for the bit fields in the NVIC_PEND1 register.
2939 #define NVIC_PEND1_INT59 0x08000000 ///< Interrupt 59 pend
2940 #define NVIC_PEND1_INT58 0x04000000 ///< Interrupt 58 pend
2941 #define NVIC_PEND1_INT57 0x02000000 ///< Interrupt 57 pend
2942 #define NVIC_PEND1_INT56 0x01000000 ///< Interrupt 56 pend
2943 #define NVIC_PEND1_INT55 0x00800000 ///< Interrupt 55 pend
2944 #define NVIC_PEND1_INT54 0x00400000 ///< Interrupt 54 pend
2945 #define NVIC_PEND1_INT53 0x00200000 ///< Interrupt 53 pend
2946 #define NVIC_PEND1_INT52 0x00100000 ///< Interrupt 52 pend
2947 #define NVIC_PEND1_INT51 0x00080000 ///< Interrupt 51 pend
2948 #define NVIC_PEND1_INT50 0x00040000 ///< Interrupt 50 pend
2949 #define NVIC_PEND1_INT49 0x00020000 ///< Interrupt 49 pend
2950 #define NVIC_PEND1_INT48 0x00010000 ///< Interrupt 48 pend
2951 #define NVIC_PEND1_INT47 0x00008000 ///< Interrupt 47 pend
2952 #define NVIC_PEND1_INT46 0x00004000 ///< Interrupt 46 pend
2953 #define NVIC_PEND1_INT45 0x00002000 ///< Interrupt 45 pend
2954 #define NVIC_PEND1_INT44 0x00001000 ///< Interrupt 44 pend
2955 #define NVIC_PEND1_INT43 0x00000800 ///< Interrupt 43 pend
2956 #define NVIC_PEND1_INT42 0x00000400 ///< Interrupt 42 pend
2957 #define NVIC_PEND1_INT41 0x00000200 ///< Interrupt 41 pend
2958 #define NVIC_PEND1_INT40 0x00000100 ///< Interrupt 40 pend
2959 #define NVIC_PEND1_INT39 0x00000080 ///< Interrupt 39 pend
2960 #define NVIC_PEND1_INT38 0x00000040 ///< Interrupt 38 pend
2961 #define NVIC_PEND1_INT37 0x00000020 ///< Interrupt 37 pend
2962 #define NVIC_PEND1_INT36 0x00000010 ///< Interrupt 36 pend
2963 #define NVIC_PEND1_INT35 0x00000008 ///< Interrupt 35 pend
2964 #define NVIC_PEND1_INT34 0x00000004 ///< Interrupt 34 pend
2965 #define NVIC_PEND1_INT33 0x00000002 ///< Interrupt 33 pend
2966 #define NVIC_PEND1_INT32 0x00000001 ///< Interrupt 32 pend
2970 * The following are defines for the bit fields in the NVIC_UNPEND0 register.
2973 #define NVIC_UNPEND0_INT31 0x80000000 ///< Interrupt 31 unpend
2974 #define NVIC_UNPEND0_INT30 0x40000000 ///< Interrupt 30 unpend
2975 #define NVIC_UNPEND0_INT29 0x20000000 ///< Interrupt 29 unpend
2976 #define NVIC_UNPEND0_INT28 0x10000000 ///< Interrupt 28 unpend
2977 #define NVIC_UNPEND0_INT27 0x08000000 ///< Interrupt 27 unpend
2978 #define NVIC_UNPEND0_INT26 0x04000000 ///< Interrupt 26 unpend
2979 #define NVIC_UNPEND0_INT25 0x02000000 ///< Interrupt 25 unpend
2980 #define NVIC_UNPEND0_INT24 0x01000000 ///< Interrupt 24 unpend
2981 #define NVIC_UNPEND0_INT23 0x00800000 ///< Interrupt 23 unpend
2982 #define NVIC_UNPEND0_INT22 0x00400000 ///< Interrupt 22 unpend
2983 #define NVIC_UNPEND0_INT21 0x00200000 ///< Interrupt 21 unpend
2984 #define NVIC_UNPEND0_INT20 0x00100000 ///< Interrupt 20 unpend
2985 #define NVIC_UNPEND0_INT19 0x00080000 ///< Interrupt 19 unpend
2986 #define NVIC_UNPEND0_INT18 0x00040000 ///< Interrupt 18 unpend
2987 #define NVIC_UNPEND0_INT17 0x00020000 ///< Interrupt 17 unpend
2988 #define NVIC_UNPEND0_INT16 0x00010000 ///< Interrupt 16 unpend
2989 #define NVIC_UNPEND0_INT15 0x00008000 ///< Interrupt 15 unpend
2990 #define NVIC_UNPEND0_INT14 0x00004000 ///< Interrupt 14 unpend
2991 #define NVIC_UNPEND0_INT13 0x00002000 ///< Interrupt 13 unpend
2992 #define NVIC_UNPEND0_INT12 0x00001000 ///< Interrupt 12 unpend
2993 #define NVIC_UNPEND0_INT11 0x00000800 ///< Interrupt 11 unpend
2994 #define NVIC_UNPEND0_INT10 0x00000400 ///< Interrupt 10 unpend
2995 #define NVIC_UNPEND0_INT9 0x00000200 ///< Interrupt 9 unpend
2996 #define NVIC_UNPEND0_INT8 0x00000100 ///< Interrupt 8 unpend
2997 #define NVIC_UNPEND0_INT7 0x00000080 ///< Interrupt 7 unpend
2998 #define NVIC_UNPEND0_INT6 0x00000040 ///< Interrupt 6 unpend
2999 #define NVIC_UNPEND0_INT5 0x00000020 ///< Interrupt 5 unpend
3000 #define NVIC_UNPEND0_INT4 0x00000010 ///< Interrupt 4 unpend
3001 #define NVIC_UNPEND0_INT3 0x00000008 ///< Interrupt 3 unpend
3002 #define NVIC_UNPEND0_INT2 0x00000004 ///< Interrupt 2 unpend
3003 #define NVIC_UNPEND0_INT1 0x00000002 ///< Interrupt 1 unpend
3004 #define NVIC_UNPEND0_INT0 0x00000001 ///< Interrupt 0 unpend
3008 * The following are defines for the bit fields in the NVIC_UNPEND1 register.
3011 #define NVIC_UNPEND1_INT59 0x08000000 ///< Interrupt 59 unpend
3012 #define NVIC_UNPEND1_INT58 0x04000000 ///< Interrupt 58 unpend
3013 #define NVIC_UNPEND1_INT57 0x02000000 ///< Interrupt 57 unpend
3014 #define NVIC_UNPEND1_INT56 0x01000000 ///< Interrupt 56 unpend
3015 #define NVIC_UNPEND1_INT55 0x00800000 ///< Interrupt 55 unpend
3016 #define NVIC_UNPEND1_INT54 0x00400000 ///< Interrupt 54 unpend
3017 #define NVIC_UNPEND1_INT53 0x00200000 ///< Interrupt 53 unpend
3018 #define NVIC_UNPEND1_INT52 0x00100000 ///< Interrupt 52 unpend
3019 #define NVIC_UNPEND1_INT51 0x00080000 ///< Interrupt 51 unpend
3020 #define NVIC_UNPEND1_INT50 0x00040000 ///< Interrupt 50 unpend
3021 #define NVIC_UNPEND1_INT49 0x00020000 ///< Interrupt 49 unpend
3022 #define NVIC_UNPEND1_INT48 0x00010000 ///< Interrupt 48 unpend
3023 #define NVIC_UNPEND1_INT47 0x00008000 ///< Interrupt 47 unpend
3024 #define NVIC_UNPEND1_INT46 0x00004000 ///< Interrupt 46 unpend
3025 #define NVIC_UNPEND1_INT45 0x00002000 ///< Interrupt 45 unpend
3026 #define NVIC_UNPEND1_INT44 0x00001000 ///< Interrupt 44 unpend
3027 #define NVIC_UNPEND1_INT43 0x00000800 ///< Interrupt 43 unpend
3028 #define NVIC_UNPEND1_INT42 0x00000400 ///< Interrupt 42 unpend
3029 #define NVIC_UNPEND1_INT41 0x00000200 ///< Interrupt 41 unpend
3030 #define NVIC_UNPEND1_INT40 0x00000100 ///< Interrupt 40 unpend
3031 #define NVIC_UNPEND1_INT39 0x00000080 ///< Interrupt 39 unpend
3032 #define NVIC_UNPEND1_INT38 0x00000040 ///< Interrupt 38 unpend
3033 #define NVIC_UNPEND1_INT37 0x00000020 ///< Interrupt 37 unpend
3034 #define NVIC_UNPEND1_INT36 0x00000010 ///< Interrupt 36 unpend
3035 #define NVIC_UNPEND1_INT35 0x00000008 ///< Interrupt 35 unpend
3036 #define NVIC_UNPEND1_INT34 0x00000004 ///< Interrupt 34 unpend
3037 #define NVIC_UNPEND1_INT33 0x00000002 ///< Interrupt 33 unpend
3038 #define NVIC_UNPEND1_INT32 0x00000001 ///< Interrupt 32 unpend
3042 * The following are defines for the bit fields in the NVIC_ACTIVE0 register.
3045 #define NVIC_ACTIVE0_INT31 0x80000000 ///< Interrupt 31 active
3046 #define NVIC_ACTIVE0_INT30 0x40000000 ///< Interrupt 30 active
3047 #define NVIC_ACTIVE0_INT29 0x20000000 ///< Interrupt 29 active
3048 #define NVIC_ACTIVE0_INT28 0x10000000 ///< Interrupt 28 active
3049 #define NVIC_ACTIVE0_INT27 0x08000000 ///< Interrupt 27 active
3050 #define NVIC_ACTIVE0_INT26 0x04000000 ///< Interrupt 26 active
3051 #define NVIC_ACTIVE0_INT25 0x02000000 ///< Interrupt 25 active
3052 #define NVIC_ACTIVE0_INT24 0x01000000 ///< Interrupt 24 active
3053 #define NVIC_ACTIVE0_INT23 0x00800000 ///< Interrupt 23 active
3054 #define NVIC_ACTIVE0_INT22 0x00400000 ///< Interrupt 22 active
3055 #define NVIC_ACTIVE0_INT21 0x00200000 ///< Interrupt 21 active
3056 #define NVIC_ACTIVE0_INT20 0x00100000 ///< Interrupt 20 active
3057 #define NVIC_ACTIVE0_INT19 0x00080000 ///< Interrupt 19 active
3058 #define NVIC_ACTIVE0_INT18 0x00040000 ///< Interrupt 18 active
3059 #define NVIC_ACTIVE0_INT17 0x00020000 ///< Interrupt 17 active
3060 #define NVIC_ACTIVE0_INT16 0x00010000 ///< Interrupt 16 active
3061 #define NVIC_ACTIVE0_INT15 0x00008000 ///< Interrupt 15 active
3062 #define NVIC_ACTIVE0_INT14 0x00004000 ///< Interrupt 14 active
3063 #define NVIC_ACTIVE0_INT13 0x00002000 ///< Interrupt 13 active
3064 #define NVIC_ACTIVE0_INT12 0x00001000 ///< Interrupt 12 active
3065 #define NVIC_ACTIVE0_INT11 0x00000800 ///< Interrupt 11 active
3066 #define NVIC_ACTIVE0_INT10 0x00000400 ///< Interrupt 10 active
3067 #define NVIC_ACTIVE0_INT9 0x00000200 ///< Interrupt 9 active
3068 #define NVIC_ACTIVE0_INT8 0x00000100 ///< Interrupt 8 active
3069 #define NVIC_ACTIVE0_INT7 0x00000080 ///< Interrupt 7 active
3070 #define NVIC_ACTIVE0_INT6 0x00000040 ///< Interrupt 6 active
3071 #define NVIC_ACTIVE0_INT5 0x00000020 ///< Interrupt 5 active
3072 #define NVIC_ACTIVE0_INT4 0x00000010 ///< Interrupt 4 active
3073 #define NVIC_ACTIVE0_INT3 0x00000008 ///< Interrupt 3 active
3074 #define NVIC_ACTIVE0_INT2 0x00000004 ///< Interrupt 2 active
3075 #define NVIC_ACTIVE0_INT1 0x00000002 ///< Interrupt 1 active
3076 #define NVIC_ACTIVE0_INT0 0x00000001 ///< Interrupt 0 active
3080 * The following are defines for the bit fields in the NVIC_ACTIVE1 register.
3083 #define NVIC_ACTIVE1_INT59 0x08000000 ///< Interrupt 59 active
3084 #define NVIC_ACTIVE1_INT58 0x04000000 ///< Interrupt 58 active
3085 #define NVIC_ACTIVE1_INT57 0x02000000 ///< Interrupt 57 active
3086 #define NVIC_ACTIVE1_INT56 0x01000000 ///< Interrupt 56 active
3087 #define NVIC_ACTIVE1_INT55 0x00800000 ///< Interrupt 55 active
3088 #define NVIC_ACTIVE1_INT54 0x00400000 ///< Interrupt 54 active
3089 #define NVIC_ACTIVE1_INT53 0x00200000 ///< Interrupt 53 active
3090 #define NVIC_ACTIVE1_INT52 0x00100000 ///< Interrupt 52 active
3091 #define NVIC_ACTIVE1_INT51 0x00080000 ///< Interrupt 51 active
3092 #define NVIC_ACTIVE1_INT50 0x00040000 ///< Interrupt 50 active
3093 #define NVIC_ACTIVE1_INT49 0x00020000 ///< Interrupt 49 active
3094 #define NVIC_ACTIVE1_INT48 0x00010000 ///< Interrupt 48 active
3095 #define NVIC_ACTIVE1_INT47 0x00008000 ///< Interrupt 47 active
3096 #define NVIC_ACTIVE1_INT46 0x00004000 ///< Interrupt 46 active
3097 #define NVIC_ACTIVE1_INT45 0x00002000 ///< Interrupt 45 active
3098 #define NVIC_ACTIVE1_INT44 0x00001000 ///< Interrupt 44 active
3099 #define NVIC_ACTIVE1_INT43 0x00000800 ///< Interrupt 43 active
3100 #define NVIC_ACTIVE1_INT42 0x00000400 ///< Interrupt 42 active
3101 #define NVIC_ACTIVE1_INT41 0x00000200 ///< Interrupt 41 active
3102 #define NVIC_ACTIVE1_INT40 0x00000100 ///< Interrupt 40 active
3103 #define NVIC_ACTIVE1_INT39 0x00000080 ///< Interrupt 39 active
3104 #define NVIC_ACTIVE1_INT38 0x00000040 ///< Interrupt 38 active
3105 #define NVIC_ACTIVE1_INT37 0x00000020 ///< Interrupt 37 active
3106 #define NVIC_ACTIVE1_INT36 0x00000010 ///< Interrupt 36 active
3107 #define NVIC_ACTIVE1_INT35 0x00000008 ///< Interrupt 35 active
3108 #define NVIC_ACTIVE1_INT34 0x00000004 ///< Interrupt 34 active
3109 #define NVIC_ACTIVE1_INT33 0x00000002 ///< Interrupt 33 active
3110 #define NVIC_ACTIVE1_INT32 0x00000001 ///< Interrupt 32 active
3114 * The following are defines for the bit fields in the NVIC_PRI0 register.
3117 #define NVIC_PRI0_INT3_M 0xFF000000 ///< Interrupt 3 priority mask
3118 #define NVIC_PRI0_INT2_M 0x00FF0000 ///< Interrupt 2 priority mask
3119 #define NVIC_PRI0_INT1_M 0x0000FF00 ///< Interrupt 1 priority mask
3120 #define NVIC_PRI0_INT0_M 0x000000FF ///< Interrupt 0 priority mask
3121 #define NVIC_PRI0_INT3_S 24
3122 #define NVIC_PRI0_INT2_S 16
3123 #define NVIC_PRI0_INT1_S 8
3124 #define NVIC_PRI0_INT0_S 0
3128 * The following are defines for the bit fields in the NVIC_PRI1 register.
3131 #define NVIC_PRI1_INT7_M 0xFF000000 ///< Interrupt 7 priority mask
3132 #define NVIC_PRI1_INT6_M 0x00FF0000 ///< Interrupt 6 priority mask
3133 #define NVIC_PRI1_INT5_M 0x0000FF00 ///< Interrupt 5 priority mask
3134 #define NVIC_PRI1_INT4_M 0x000000FF ///< Interrupt 4 priority mask
3135 #define NVIC_PRI1_INT7_S 24
3136 #define NVIC_PRI1_INT6_S 16
3137 #define NVIC_PRI1_INT5_S 8
3138 #define NVIC_PRI1_INT4_S 0
3142 * The following are defines for the bit fields in the NVIC_PRI2 register.
3145 #define NVIC_PRI2_INT11_M 0xFF000000 ///< Interrupt 11 priority mask
3146 #define NVIC_PRI2_INT10_M 0x00FF0000 ///< Interrupt 10 priority mask
3147 #define NVIC_PRI2_INT9_M 0x0000FF00 ///< Interrupt 9 priority mask
3148 #define NVIC_PRI2_INT8_M 0x000000FF ///< Interrupt 8 priority mask
3149 #define NVIC_PRI2_INT11_S 24
3150 #define NVIC_PRI2_INT10_S 16
3151 #define NVIC_PRI2_INT9_S 8
3152 #define NVIC_PRI2_INT8_S 0
3156 * The following are defines for the bit fields in the NVIC_PRI3 register.
3159 #define NVIC_PRI3_INT15_M 0xFF000000 ///< Interrupt 15 priority mask
3160 #define NVIC_PRI3_INT14_M 0x00FF0000 ///< Interrupt 14 priority mask
3161 #define NVIC_PRI3_INT13_M 0x0000FF00 ///< Interrupt 13 priority mask
3162 #define NVIC_PRI3_INT12_M 0x000000FF ///< Interrupt 12 priority mask
3163 #define NVIC_PRI3_INT15_S 24
3164 #define NVIC_PRI3_INT14_S 16
3165 #define NVIC_PRI3_INT13_S 8
3166 #define NVIC_PRI3_INT12_S 0
3170 * The following are defines for the bit fields in the NVIC_PRI4 register.
3173 #define NVIC_PRI4_INT19_M 0xFF000000 ///< Interrupt 19 priority mask
3174 #define NVIC_PRI4_INT18_M 0x00FF0000 ///< Interrupt 18 priority mask
3175 #define NVIC_PRI4_INT17_M 0x0000FF00 ///< Interrupt 17 priority mask
3176 #define NVIC_PRI4_INT16_M 0x000000FF ///< Interrupt 16 priority mask
3177 #define NVIC_PRI4_INT19_S 24
3178 #define NVIC_PRI4_INT18_S 16
3179 #define NVIC_PRI4_INT17_S 8
3180 #define NVIC_PRI4_INT16_S 0
3184 * The following are defines for the bit fields in the NVIC_PRI5 register.
3187 #define NVIC_PRI5_INT23_M 0xFF000000 ///< Interrupt 23 priority mask
3188 #define NVIC_PRI5_INT22_M 0x00FF0000 ///< Interrupt 22 priority mask
3189 #define NVIC_PRI5_INT21_M 0x0000FF00 ///< Interrupt 21 priority mask
3190 #define NVIC_PRI5_INT20_M 0x000000FF ///< Interrupt 20 priority mask
3191 #define NVIC_PRI5_INT23_S 24
3192 #define NVIC_PRI5_INT22_S 16
3193 #define NVIC_PRI5_INT21_S 8
3194 #define NVIC_PRI5_INT20_S 0
3198 * The following are defines for the bit fields in the NVIC_PRI6 register.
3201 #define NVIC_PRI6_INT27_M 0xFF000000 ///< Interrupt 27 priority mask
3202 #define NVIC_PRI6_INT26_M 0x00FF0000 ///< Interrupt 26 priority mask
3203 #define NVIC_PRI6_INT25_M 0x0000FF00 ///< Interrupt 25 priority mask
3204 #define NVIC_PRI6_INT24_M 0x000000FF ///< Interrupt 24 priority mask
3205 #define NVIC_PRI6_INT27_S 24
3206 #define NVIC_PRI6_INT26_S 16
3207 #define NVIC_PRI6_INT25_S 8
3208 #define NVIC_PRI6_INT24_S 0
3212 * The following are defines for the bit fields in the NVIC_PRI7 register.
3215 #define NVIC_PRI7_INT31_M 0xFF000000 ///< Interrupt 31 priority mask
3216 #define NVIC_PRI7_INT30_M 0x00FF0000 ///< Interrupt 30 priority mask
3217 #define NVIC_PRI7_INT29_M 0x0000FF00 ///< Interrupt 29 priority mask
3218 #define NVIC_PRI7_INT28_M 0x000000FF ///< Interrupt 28 priority mask
3219 #define NVIC_PRI7_INT31_S 24
3220 #define NVIC_PRI7_INT30_S 16
3221 #define NVIC_PRI7_INT29_S 8
3222 #define NVIC_PRI7_INT28_S 0
3226 * The following are defines for the bit fields in the NVIC_PRI8 register.
3229 #define NVIC_PRI8_INT35_M 0xFF000000 ///< Interrupt 35 priority mask
3230 #define NVIC_PRI8_INT34_M 0x00FF0000 ///< Interrupt 34 priority mask
3231 #define NVIC_PRI8_INT33_M 0x0000FF00 ///< Interrupt 33 priority mask
3232 #define NVIC_PRI8_INT32_M 0x000000FF ///< Interrupt 32 priority mask
3233 #define NVIC_PRI8_INT35_S 24
3234 #define NVIC_PRI8_INT34_S 16
3235 #define NVIC_PRI8_INT33_S 8
3236 #define NVIC_PRI8_INT32_S 0
3240 * The following are defines for the bit fields in the NVIC_PRI9 register.
3243 #define NVIC_PRI9_INT39_M 0xFF000000 ///< Interrupt 39 priority mask
3244 #define NVIC_PRI9_INT38_M 0x00FF0000 ///< Interrupt 38 priority mask
3245 #define NVIC_PRI9_INT37_M 0x0000FF00 ///< Interrupt 37 priority mask
3246 #define NVIC_PRI9_INT36_M 0x000000FF ///< Interrupt 36 priority mask
3247 #define NVIC_PRI9_INT39_S 24
3248 #define NVIC_PRI9_INT38_S 16
3249 #define NVIC_PRI9_INT37_S 8
3250 #define NVIC_PRI9_INT36_S 0
3254 * The following are defines for the bit fields in the NVIC_PRI10 register.
3257 #define NVIC_PRI10_INT43_M 0xFF000000 ///< Interrupt 43 priority mask
3258 #define NVIC_PRI10_INT42_M 0x00FF0000 ///< Interrupt 42 priority mask
3259 #define NVIC_PRI10_INT41_M 0x0000FF00 ///< Interrupt 41 priority mask
3260 #define NVIC_PRI10_INT40_M 0x000000FF ///< Interrupt 40 priority mask
3261 #define NVIC_PRI10_INT43_S 24
3262 #define NVIC_PRI10_INT42_S 16
3263 #define NVIC_PRI10_INT41_S 8
3264 #define NVIC_PRI10_INT40_S 0
3268 * The following are defines for the bit fields in the NVIC_CPUID register.
3271 #define NVIC_CPUID_IMP_M 0xFF000000 ///< Implementer
3272 #define NVIC_CPUID_VAR_M 0x00F00000 ///< Variant
3273 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 ///< Processor part number
3274 #define NVIC_CPUID_REV_M 0x0000000F ///< Revision
3278 * The following are defines for the bit fields in the NVIC_INT_CTRL register.
3281 #define NVIC_INT_CTRL_NMI_SET 0x80000000 ///< Pend a NMI
3282 #define NVIC_INT_CTRL_PEND_SV 0x10000000 ///< Pend a PendSV
3283 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 ///< Unpend a PendSV
3284 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 ///< Set pending SysTick interrupt
3285 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 ///< Clear pending SysTick interrupt
3286 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 ///< Debug interrupt handling
3287 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 ///< Debug interrupt pending
3288 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 ///< Highest pending exception
3289 #define NVIC_INT_CTRL_RET_BASE 0x00000800 ///< Return to base
3290 #define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF ///< Current active exception
3291 #define NVIC_INT_CTRL_VEC_PEN_S 12
3292 #define NVIC_INT_CTRL_VEC_ACT_S 0
3296 * The following are defines for the bit fields in the NVIC_VTABLE register.
3299 #define NVIC_VTABLE_BASE 0x20000000 ///< Vector table base
3300 #define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 ///< Vector table offset
3301 #define NVIC_VTABLE_OFFSET_S 8
3305 * The following are defines for the bit fields in the NVIC_APINT register.
3308 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 ///< Vector key mask
3309 #define NVIC_APINT_VECTKEY 0x05FA0000 ///< Vector key
3310 #define NVIC_APINT_ENDIANESS 0x00008000 ///< Data endianess
3311 #define NVIC_APINT_PRIGROUP_M 0x00000700 ///< Priority group
3312 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 ///< Priority group 0.8 split
3313 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 ///< Priority group 1.7 split
3314 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 ///< Priority group 2.6 split
3315 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 ///< Priority group 3.5 split
3316 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 ///< Priority group 4.4 split
3317 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 ///< Priority group 5.3 split
3318 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 ///< Priority group 6.2 split
3319 #define NVIC_APINT_SYSRESETREQ 0x00000004 ///< System reset request
3320 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 ///< Clear active NMI/fault info
3321 #define NVIC_APINT_VECT_RESET 0x00000001 ///< System reset
3322 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 ///< Priority group 7.1 split
3326 * The following are defines for the bit fields in the NVIC_SYS_CTRL register.
3329 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 ///< Wakeup on pend
3330 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 ///< Deep sleep enable
3331 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 ///< Sleep on ISR exit
3335 * The following are defines for the bit fields in the NVIC_CFG_CTRL register.
3338 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 ///< Ignore bus fault in NMI/fault
3339 #define NVIC_CFG_CTRL_DIV0 0x00000010 ///< Trap on divide by 0
3340 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 ///< Trap on unaligned access
3341 #define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 ///< Allow deep interrupt trigger
3342 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 ///< Allow main interrupt trigger
3343 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 ///< Thread state control
3347 * The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
3350 #define NVIC_SYS_PRI1_RES_M 0xFF000000 ///< Priority of reserved handler
3351 #define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 ///< Priority of usage fault handler
3352 #define NVIC_SYS_PRI1_BUS_M 0x0000FF00 ///< Priority of bus fault handler
3353 #define NVIC_SYS_PRI1_MEM_M 0x000000FF ///< Priority of mem manage handler
3354 #define NVIC_SYS_PRI1_USAGE_S 16
3355 #define NVIC_SYS_PRI1_BUS_S 8
3356 #define NVIC_SYS_PRI1_MEM_S 0
3360 * The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
3363 #define NVIC_SYS_PRI2_SVC_M 0xFF000000 ///< Priority of SVCall handler
3364 #define NVIC_SYS_PRI2_RES_M 0x00FFFFFF ///< Priority of reserved handlers
3365 #define NVIC_SYS_PRI2_SVC_S 24
3369 * The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
3372 #define NVIC_SYS_PRI3_TICK_M 0xFF000000 ///< Priority of Sys Tick handler
3373 #define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 ///< Priority of PendSV handler
3374 #define NVIC_SYS_PRI3_RES_M 0x0000FF00 ///< Priority of reserved handler
3375 #define NVIC_SYS_PRI3_DEBUG_M 0x000000FF ///< Priority of debug handler
3376 #define NVIC_SYS_PRI3_TICK_S 24
3377 #define NVIC_SYS_PRI3_PENDSV_S 16
3378 #define NVIC_SYS_PRI3_DEBUG_S 0
3382 * The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
3386 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 ///< Usage fault enable
3387 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 ///< Bus fault enable
3388 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 ///< Mem manage fault enable
3389 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 ///< SVCall is pended
3390 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 ///< Bus fault is pended
3391 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 ///< Sys tick is active
3392 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 ///< PendSV is active
3393 #define NVIC_SYS_HND_CTRL_MON 0x00000100 ///< Monitor is active
3394 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 ///< SVCall is active
3395 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 ///< Usage fault is active
3396 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 ///< Bus fault is active
3397 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 ///< Mem manage is active
3401 * The following are defines for the bit fields in the NVIC_FAULT_STAT
3405 #define NVIC_FAULT_STAT_DIV0 0x02000000 ///< Divide by zero fault
3406 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 ///< Unaligned access fault
3407 #define NVIC_FAULT_STAT_NOCP 0x00080000 ///< No coprocessor fault
3408 #define NVIC_FAULT_STAT_INVPC 0x00040000 ///< Invalid PC fault
3409 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 ///< Invalid state fault
3410 #define NVIC_FAULT_STAT_UNDEF 0x00010000 ///< Undefined instruction fault
3411 #define NVIC_FAULT_STAT_BFARV 0x00008000 ///< BFAR is valid
3412 #define NVIC_FAULT_STAT_BSTKE 0x00001000 ///< Stack bus fault
3413 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 ///< Unstack bus fault
3414 #define NVIC_FAULT_STAT_IMPRE 0x00000400 ///< Imprecise data bus error
3415 #define NVIC_FAULT_STAT_PRECISE 0x00000200 ///< Precise data bus error
3416 #define NVIC_FAULT_STAT_IBUS 0x00000100 ///< Instruction bus fault
3417 #define NVIC_FAULT_STAT_MMARV 0x00000080 ///< MMAR is valid
3418 #define NVIC_FAULT_STAT_MSTKE 0x00000010 ///< Stack access violation
3419 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 ///< Unstack access violation
3420 #define NVIC_FAULT_STAT_DERR 0x00000002 ///< Data access violation
3421 #define NVIC_FAULT_STAT_IERR 0x00000001 ///< Instruction access violation
3425 * The following are defines for the bit fields in the NVIC_HFAULT_STAT
3429 #define NVIC_HFAULT_STAT_DBG 0x80000000 ///< Debug event
3430 #define NVIC_HFAULT_STAT_FORCED 0x40000000 ///< Cannot execute fault handler
3431 #define NVIC_HFAULT_STAT_VECT 0x00000002 ///< Vector table read fault
3435 * The following are defines for the bit fields in the NVIC_DEBUG_STAT
3439 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 ///< EDBGRQ asserted
3440 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 ///< Vector catch
3441 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 ///< DWT match
3442 #define NVIC_DEBUG_STAT_BKPT 0x00000002 ///< Breakpoint instruction
3443 #define NVIC_DEBUG_STAT_HALTED 0x00000001 ///< Halt request
3447 * The following are defines for the bit fields in the NVIC_MM_ADDR register.
3450 #define NVIC_MM_ADDR_M 0xFFFFFFFF ///< Data fault address
3451 #define NVIC_MM_ADDR_S 0
3455 * The following are defines for the bit fields in the NVIC_FAULT_ADDR
3459 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF ///< Data bus fault address
3460 #define NVIC_FAULT_ADDR_S 0
3464 * The following are defines for the bit fields in the NVIC_MPU_TYPE register.
3467 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 ///< Number of I regions
3468 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 ///< Number of D regions
3469 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 ///< Separate or unified MPU
3470 #define NVIC_MPU_TYPE_IREGION_S 16
3471 #define NVIC_MPU_TYPE_DREGION_S 8
3475 * The following are defines for the bit fields in the NVIC_MPU_CTRL register.
3478 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 ///< MPU default region in priv mode
3479 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 ///< MPU enabled during faults
3480 #define NVIC_MPU_CTRL_ENABLE 0x00000001 ///< MPU enable
3484 * The following are defines for the bit fields in the NVIC_MPU_NUMBER
3488 #define NVIC_MPU_NUMBER_M 0x000000FF ///< MPU region to access
3489 #define NVIC_MPU_NUMBER_S 0
3493 * The following are defines for the bit fields in the NVIC_MPU_BASE register.
3496 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 ///< Base address mask
3497 #define NVIC_MPU_BASE_VALID 0x00000010 ///< Region number valid
3498 #define NVIC_MPU_BASE_REGION_M 0x0000000F ///< Region number
3499 #define NVIC_MPU_BASE_ADDR_S 8
3500 #define NVIC_MPU_BASE_REGION_S 0
3504 * The following are defines for the bit fields in the NVIC_MPU_ATTR register.
3507 #define NVIC_MPU_ATTR_M 0xFFFF0000 ///< Attributes
3508 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 ///< prv: no access, usr: no access
3509 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 ///< Bufferable
3510 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 ///< Cacheable
3511 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 ///< Shareable
3512 #define NVIC_MPU_ATTR_TEX_M 0x00380000 ///< Type extension mask
3513 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 ///< prv: rw, usr: none
3514 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 ///< prv: rw, usr: read-only
3515 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 ///< prv: rw, usr: rw
3516 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 ///< prv: ro, usr: none
3517 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 ///< prv: ro, usr: ro
3518 #define NVIC_MPU_ATTR_AP_M 0x07000000 ///< Access permissions mask
3519 #define NVIC_MPU_ATTR_XN 0x10000000 ///< Execute disable
3520 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 ///< Sub-region disable mask
3521 #define NVIC_MPU_ATTR_SRD_0 0x00000100 ///< Sub-region 0 disable
3522 #define NVIC_MPU_ATTR_SRD_1 0x00000200 ///< Sub-region 1 disable
3523 #define NVIC_MPU_ATTR_SRD_2 0x00000400 ///< Sub-region 2 disable
3524 #define NVIC_MPU_ATTR_SRD_3 0x00000800 ///< Sub-region 3 disable
3525 #define NVIC_MPU_ATTR_SRD_4 0x00001000 ///< Sub-region 4 disable
3526 #define NVIC_MPU_ATTR_SRD_5 0x00002000 ///< Sub-region 5 disable
3527 #define NVIC_MPU_ATTR_SRD_6 0x00004000 ///< Sub-region 6 disable
3528 #define NVIC_MPU_ATTR_SRD_7 0x00008000 ///< Sub-region 7 disable
3529 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E ///< Region size mask
3530 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 ///< Region size 32 bytes
3531 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A ///< Region size 64 bytes
3532 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C ///< Region size 128 bytes
3533 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E ///< Region size 256 bytes
3534 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 ///< Region size 512 bytes
3535 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 ///< Region size 1 Kbytes
3536 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 ///< Region size 2 Kbytes
3537 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 ///< Region size 4 Kbytes
3538 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 ///< Region size 8 Kbytes
3539 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A ///< Region size 16 Kbytes
3540 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C ///< Region size 32 Kbytes
3541 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E ///< Region size 64 Kbytes
3542 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 ///< Region size 128 Kbytes
3543 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 ///< Region size 256 Kbytes
3544 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 ///< Region size 512 Kbytes
3545 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 ///< Region size 1 Mbytes
3546 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 ///< Region size 2 Mbytes
3547 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A ///< Region size 4 Mbytes
3548 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C ///< Region size 8 Mbytes
3549 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E ///< Region size 16 Mbytes
3550 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 ///< Region size 32 Mbytes
3551 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 ///< Region size 64 Mbytes
3552 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 ///< Region size 128 Mbytes
3553 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 ///< Region size 256 Mbytes
3554 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 ///< Region size 512 Mbytes
3555 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A ///< Region size 1 Gbytes
3556 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C ///< Region size 2 Gbytes
3557 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E ///< Region size 4 Gbytes
3558 #define NVIC_MPU_ATTR_ENABLE 0x00000001 ///< Region enable
3562 * The following are defines for the bit fields in the NVIC_DBG_CTRL register.
3565 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 ///< Debug key mask
3566 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 ///< Debug key
3567 #define NVIC_DBG_CTRL_S_RESET_ST \
3568 0x02000000 ///< Core has reset since last read
3569 #define NVIC_DBG_CTRL_S_RETIRE_ST \
3570 0x01000000 ///< Core has executed insruction
3571 ///< since last read
3572 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 ///< Core is locked up
3573 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 ///< Core is sleeping
3574 #define NVIC_DBG_CTRL_S_HALT 0x00020000 ///< Core status on halt
3575 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 ///< Register read/write available
3576 #define NVIC_DBG_CTRL_C_SNAPSTALL \
3577 0x00000020 ///< Breaks a stalled load/store
3578 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 ///< Mask interrupts when stepping
3579 #define NVIC_DBG_CTRL_C_STEP 0x00000004 ///< Step the core
3580 #define NVIC_DBG_CTRL_C_HALT 0x00000002 ///< Halt the core
3581 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 ///< Enable debug
3585 * The following are defines for the bit fields in the NVIC_DBG_XFER register.
3588 #define NVIC_DBG_XFER_REG_WNR 0x00010000 ///< Write or not read
3589 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F ///< Register
3590 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 ///< Control/Fault/BasePri/PriMask
3591 #define NVIC_DBG_XFER_REG_DSP 0x00000013 ///< Deep SP
3592 #define NVIC_DBG_XFER_REG_PSP 0x00000012 ///< Process SP
3593 #define NVIC_DBG_XFER_REG_MSP 0x00000011 ///< Main SP
3594 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 ///< xPSR/Flags register
3595 #define NVIC_DBG_XFER_REG_R15 0x0000000F ///< Register R15
3596 #define NVIC_DBG_XFER_REG_R14 0x0000000E ///< Register R14
3597 #define NVIC_DBG_XFER_REG_R13 0x0000000D ///< Register R13
3598 #define NVIC_DBG_XFER_REG_R12 0x0000000C ///< Register R12
3599 #define NVIC_DBG_XFER_REG_R11 0x0000000B ///< Register R11
3600 #define NVIC_DBG_XFER_REG_R10 0x0000000A ///< Register R10
3601 #define NVIC_DBG_XFER_REG_R9 0x00000009 ///< Register R9
3602 #define NVIC_DBG_XFER_REG_R8 0x00000008 ///< Register R8
3603 #define NVIC_DBG_XFER_REG_R7 0x00000007 ///< Register R7
3604 #define NVIC_DBG_XFER_REG_R6 0x00000006 ///< Register R6
3605 #define NVIC_DBG_XFER_REG_R5 0x00000005 ///< Register R5
3606 #define NVIC_DBG_XFER_REG_R4 0x00000004 ///< Register R4
3607 #define NVIC_DBG_XFER_REG_R3 0x00000003 ///< Register R3
3608 #define NVIC_DBG_XFER_REG_R2 0x00000002 ///< Register R2
3609 #define NVIC_DBG_XFER_REG_R1 0x00000001 ///< Register R1
3610 #define NVIC_DBG_XFER_REG_R0 0x00000000 ///< Register R0
3614 * The following are defines for the bit fields in the NVIC_DBG_DATA register.
3617 #define NVIC_DBG_DATA_M 0xFFFFFFFF ///< Data temporary cache
3618 #define NVIC_DBG_DATA_S 0
3622 * The following are defines for the bit fields in the NVIC_DBG_INT register.
3625 #define NVIC_DBG_INT_HARDERR 0x00000400 ///< Debug trap on hard fault
3626 #define NVIC_DBG_INT_INTERR 0x00000200 ///< Debug trap on interrupt errors
3627 #define NVIC_DBG_INT_BUSERR 0x00000100 ///< Debug trap on bus error
3628 #define NVIC_DBG_INT_STATERR 0x00000080 ///< Debug trap on usage fault state
3629 #define NVIC_DBG_INT_CHKERR 0x00000040 ///< Debug trap on usage fault check
3630 #define NVIC_DBG_INT_NOCPERR 0x00000020 ///< Debug trap on coprocessor error
3631 #define NVIC_DBG_INT_MMERR 0x00000010 ///< Debug trap on mem manage fault
3632 #define NVIC_DBG_INT_RESET 0x00000008 ///< Core reset status
3633 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 ///< Clear pending core reset
3634 #define NVIC_DBG_INT_RSTPENDING 0x00000002 ///< Core reset is pending
3635 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 ///< Reset vector catch
3639 * The following are defines for the bit fields in the NVIC_SW_TRIG register.
3642 #define NVIC_SW_TRIG_INTID_M 0x000003FF ///< Interrupt to trigger
3643 #define NVIC_SW_TRIG_INTID_S 0
3647 * The following definitions are deprecated.
3652 * Deprecated defines for the Watchdog
3655 #define WATCHDOG_LOAD_R (*((reg32_t *)0x40000000))
3656 #define WATCHDOG_VALUE_R (*((reg32_t *)0x40000004))
3657 #define WATCHDOG_CTL_R (*((reg32_t *)0x40000008))
3658 #define WATCHDOG_ICR_R (*((reg32_t *)0x4000000C))
3659 #define WATCHDOG_RIS_R (*((reg32_t *)0x40000010))
3660 #define WATCHDOG_MIS_R (*((reg32_t *)0x40000014))
3661 #define WATCHDOG_TEST_R (*((reg32_t *)0x40000418))
3662 #define WATCHDOG_LOCK_R (*((reg32_t *)0x40000C00))
3666 * Deprecated defines for the bit fields in the I2C_O_SICR register.
3669 #define I2C_SICR_IC 0x00000001 ///< Clear Interrupt
3673 * Deprecated defines for the bit fields in the I2C_O_SMIS register.
3676 #define I2C_SMIS_MIS 0x00000001 ///< Masked Interrupt Status
3680 * Deprecated defines for the bit fields in the I2C_O_SRIS register.
3683 #define I2C_SRIS_RIS 0x00000001 ///< Raw Interrupt Status
3687 * Deprecated defines for the bit fields in the I2C_O_SIMR register.
3690 #define I2C_SIMR_IM 0x00000001 ///< Interrupt Mask
3694 * Deprecated defines for the bit fields in the the interpretation of the data
3695 * in the SSFIFOx when the ADC TMLB is enabled. register.
3698 #define ADC_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
3699 #define ADC_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
3700 #define ADC_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
3701 #define ADC_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
3702 #define ADC_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
3703 #define ADC_TMLB_CNT_S 6 ///< Sample counter shift
3704 #define ADC_TMLB_MUX_S 0 ///< Input channel number shift
3708 * Deprecated defines for the ADC register offsets.
3711 #define ADC_ACTSS_R (*((reg32_t *)0x40038000))
3712 #define ADC_RIS_R (*((reg32_t *)0x40038004))
3713 #define ADC_IM_R (*((reg32_t *)0x40038008))
3714 #define ADC_ISC_R (*((reg32_t *)0x4003800C))
3715 #define ADC_OSTAT_R (*((reg32_t *)0x40038010))
3716 #define ADC_EMUX_R (*((reg32_t *)0x40038014))
3717 #define ADC_USTAT_R (*((reg32_t *)0x40038018))
3718 #define ADC_SSPRI_R (*((reg32_t *)0x40038020))
3719 #define ADC_PSSI_R (*((reg32_t *)0x40038028))
3720 #define ADC_SAC_R (*((reg32_t *)0x40038030))
3721 #define ADC_SSMUX0_R (*((reg32_t *)0x40038040))
3722 #define ADC_SSCTL0_R (*((reg32_t *)0x40038044))
3723 #define ADC_SSFIFO0_R (*((reg32_t *)0x40038048))
3724 #define ADC_SSFSTAT0_R (*((reg32_t *)0x4003804C))
3725 #define ADC_SSMUX1_R (*((reg32_t *)0x40038060))
3726 #define ADC_SSCTL1_R (*((reg32_t *)0x40038064))
3727 #define ADC_SSFIFO1_R (*((reg32_t *)0x40038068))
3728 #define ADC_SSFSTAT1_R (*((reg32_t *)0x4003806C))
3729 #define ADC_SSMUX2_R (*((reg32_t *)0x40038080))
3730 #define ADC_SSCTL2_R (*((reg32_t *)0x40038084))
3731 #define ADC_SSFIFO2_R (*((reg32_t *)0x40038088))
3732 #define ADC_SSFSTAT2_R (*((reg32_t *)0x4003808C))
3733 #define ADC_SSMUX3_R (*((reg32_t *)0x400380A0))
3734 #define ADC_SSCTL3_R (*((reg32_t *)0x400380A4))
3735 #define ADC_SSFIFO3_R (*((reg32_t *)0x400380A8))
3736 #define ADC_SSFSTAT3_R (*((reg32_t *)0x400380AC))
3737 #define ADC_TMLB_R (*((reg32_t *)0x40038100))
3741 * Deprecated defines for the bit fields in the FLASH_FMC register.
3744 #define FLASH_FMC_WRKEY_M 0xFFFF0000 ///< Flash Memory Write Key
3745 #define FLASH_FMC_WRKEY_S 16
3749 * Deprecated defines for the bit fields in the SYSCTL_DID1 register.
3752 #define SYSCTL_DID1_PKG_28SOIC 0x00000000 ///< SOIC package
3753 #define SYSCTL_DID1_PKG_48QFP 0x00000008 ///< QFP package
3757 * Deprecated defines for the NVIC register addresses.
3760 #define NVIC_MPU_R (*((reg32_t *)0xE000ED9C))
3763 #endif /* DEPRECATED */
3765 #endif /* LM3S1968_H */