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33 * \brief LM3S ADC definition.
41 * The following are defines for the ADC register offsets.
43 #define ADC_O_ACTSS 0x00000000 ///< ADC Active Sample Sequencer
44 #define ADC_O_RIS 0x00000004 ///< ADC Raw Interrupt Status
45 #define ADC_O_IM 0x00000008 ///< ADC Interrupt Mask
46 #define ADC_O_ISC 0x0000000C ///< ADC Interrupt Status and Clear
47 #define ADC_O_OSTAT 0x00000010 ///< ADC Overflow Status
48 #define ADC_O_EMUX 0x00000014 ///< ADC Event Multiplexer Select
49 #define ADC_O_USTAT 0x00000018 ///< ADC Underflow Status
50 #define ADC_O_SSPRI 0x00000020 ///< ADC Sample Sequencer Priority
51 #define ADC_O_SPC 0x00000024 ///< ADC Sample Phase Control
52 #define ADC_O_PSSI 0x00000028 ///< ADC Processor Sample Sequence
54 #define ADC_O_SAC 0x00000030 ///< ADC Sample Averaging Control
55 #define ADC_O_DCISC 0x00000034 ///< ADC Digital Comparator Interrupt
57 #define ADC_O_CTL 0x00000038 ///< ADC Control
58 #define ADC_O_SSMUX0 0x00000040 ///< ADC Sample Sequence Input
59 ///< Multiplexer Select 0
60 #define ADC_O_SSCTL0 0x00000044 ///< ADC Sample Sequence Control 0
61 #define ADC_O_SSFIFO0 0x00000048 ///< ADC Sample Sequence Result FIFO
63 #define ADC_O_SSFSTAT0 0x0000004C ///< ADC Sample Sequence FIFO 0
65 #define ADC_O_SSOP0 0x00000050 ///< ADC Sample Sequence 0 Operation
66 #define ADC_O_SSDC0 0x00000054 ///< ADC Sample Sequence 0 Digital
67 ///< Comparator Select
68 #define ADC_O_SSMUX1 0x00000060 ///< ADC Sample Sequence Input
69 ///< Multiplexer Select 1
70 #define ADC_O_SSCTL1 0x00000064 ///< ADC Sample Sequence Control 1
71 #define ADC_O_SSFIFO1 0x00000068 ///< ADC Sample Sequence Result FIFO
73 #define ADC_O_SSFSTAT1 0x0000006C ///< ADC Sample Sequence FIFO 1
75 #define ADC_O_SSOP1 0x00000070 ///< ADC Sample Sequence 1 Operation
76 #define ADC_O_SSDC1 0x00000074 ///< ADC Sample Sequence 1 Digital
77 ///< Comparator Select
78 #define ADC_O_SSMUX2 0x00000080 ///< ADC Sample Sequence Input
79 ///< Multiplexer Select 2
80 #define ADC_O_SSCTL2 0x00000084 ///< ADC Sample Sequence Control 2
81 #define ADC_O_SSFIFO2 0x00000088 ///< ADC Sample Sequence Result FIFO
83 #define ADC_O_SSFSTAT2 0x0000008C ///< ADC Sample Sequence FIFO 2
85 #define ADC_O_SSOP2 0x00000090 ///< ADC Sample Sequence 2 Operation
86 #define ADC_O_SSDC2 0x00000094 ///< ADC Sample Sequence 2 Digital
87 ///< Comparator Select
88 #define ADC_O_SSMUX3 0x000000A0 ///< ADC Sample Sequence Input
89 ///< Multiplexer Select 3
90 #define ADC_O_SSCTL3 0x000000A4 ///< ADC Sample Sequence Control 3
91 #define ADC_O_SSFIFO3 0x000000A8 ///< ADC Sample Sequence Result FIFO
93 #define ADC_O_SSFSTAT3 0x000000AC ///< ADC Sample Sequence FIFO 3
95 #define ADC_O_SSOP3 0x000000B0 ///< ADC Sample Sequence 3 Operation
96 #define ADC_O_SSDC3 0x000000B4 ///< ADC Sample Sequence 3 Digital
97 ///< Comparator Select
98 #define ADC_O_TMLB 0x00000100 ///< ADC Test Mode Loopback
99 #define ADC_O_DCRIC 0x00000D00 ///< ADC Digital Comparator Reset
100 ///< Initial Conditions
101 #define ADC_O_DCCTL0 0x00000E00 ///< ADC Digital Comparator Control 0
102 #define ADC_O_DCCTL1 0x00000E04 ///< ADC Digital Comparator Control 1
103 #define ADC_O_DCCTL2 0x00000E08 ///< ADC Digital Comparator Control 2
104 #define ADC_O_DCCTL3 0x00000E0C ///< ADC Digital Comparator Control 3
105 #define ADC_O_DCCTL4 0x00000E10 ///< ADC Digital Comparator Control 4
106 #define ADC_O_DCCTL5 0x00000E14 ///< ADC Digital Comparator Control 5
107 #define ADC_O_DCCTL6 0x00000E18 ///< ADC Digital Comparator Control 6
108 #define ADC_O_DCCTL7 0x00000E1C ///< ADC Digital Comparator Control 7
109 #define ADC_O_DCCMP0 0x00000E40 ///< ADC Digital Comparator Range 0
110 #define ADC_O_DCCMP1 0x00000E44 ///< ADC Digital Comparator Range 1
111 #define ADC_O_DCCMP2 0x00000E48 ///< ADC Digital Comparator Range 2
112 #define ADC_O_DCCMP3 0x00000E4C ///< ADC Digital Comparator Range 3
113 #define ADC_O_DCCMP4 0x00000E50 ///< ADC Digital Comparator Range 4
114 #define ADC_O_DCCMP5 0x00000E54 ///< ADC Digital Comparator Range 5
115 #define ADC_O_DCCMP6 0x00000E58 ///< ADC Digital Comparator Range 6
116 #define ADC_O_DCCMP7 0x00000E5C ///< ADC Digital Comparator Range 7
120 * The following are defines for the bit fields in the ADC_O_ACTSS register.
122 #define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable
123 #define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable
124 #define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable
125 #define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable
129 * The following are defines for the bit fields in the ADC_O_RIS register.
131 #define ADC_RIS_INRDC 0x00010000 ///< Digital Comparator Raw Interrupt
133 #define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status
134 #define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status
135 #define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status
136 #define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status
140 * The following are defines for the bit fields in the ADC_O_IM register.
142 #define ADC_IM_DCONSS3 0x00080000 ///< Digital Comparator Interrupt on
144 #define ADC_IM_DCONSS2 0x00040000 ///< Digital Comparator Interrupt on
146 #define ADC_IM_DCONSS1 0x00020000 ///< Digital Comparator Interrupt on
148 #define ADC_IM_DCONSS0 0x00010000 ///< Digital Comparator Interrupt on
150 #define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask
151 #define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask
152 #define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask
153 #define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask
157 * The following are defines for the bit fields in the ADC_O_ISC register.
159 #define ADC_ISC_DCINSS3 0x00080000 ///< Digital Comparator Interrupt
161 #define ADC_ISC_DCINSS2 0x00040000 ///< Digital Comparator Interrupt
163 #define ADC_ISC_DCINSS1 0x00020000 ///< Digital Comparator Interrupt
165 #define ADC_ISC_DCINSS0 0x00010000 ///< Digital Comparator Interrupt
167 #define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear
168 #define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear
169 #define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear
170 #define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear
174 * The following are defines for the bit fields in the ADC_O_OSTAT register.
176 #define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow
177 #define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow
178 #define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow
179 #define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow
183 * The following are defines for the bit fields in the ADC_O_EMUX register.
185 #define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select
186 #define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default)
187 #define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0
188 #define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1
189 #define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2
190 #define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4)
191 #define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer
192 #define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0
193 #define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1
194 #define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2
195 #define ADC_EMUX_EM3_PWM3 0x00009000 ///< PWM3
196 #define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample)
197 #define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select
198 #define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default)
199 #define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0
200 #define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1
201 #define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2
202 #define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4)
203 #define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer
204 #define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0
205 #define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1
206 #define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2
207 #define ADC_EMUX_EM2_PWM3 0x00000900 ///< PWM3
208 #define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample)
209 #define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select
210 #define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default)
211 #define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0
212 #define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1
213 #define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2
214 #define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4)
215 #define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer
216 #define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0
217 #define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1
218 #define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2
219 #define ADC_EMUX_EM1_PWM3 0x00000090 ///< PWM3
220 #define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample)
221 #define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select
222 #define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default)
223 #define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0
224 #define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1
225 #define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2
226 #define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4)
227 #define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer
228 #define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0
229 #define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1
230 #define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2
231 #define ADC_EMUX_EM0_PWM3 0x00000009 ///< PWM3
232 #define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample)
236 * The following are defines for the bit fields in the ADC_O_USTAT register.
238 #define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow
239 #define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow
240 #define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow
241 #define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow
245 * The following are defines for the bit fields in the ADC_O_SSPRI register.
247 #define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority
248 #define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority
249 #define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority
250 #define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority
251 #define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority
252 #define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority
253 #define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority
254 #define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority
255 #define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority
256 #define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority
257 #define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority
258 #define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority
259 #define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority
260 #define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority
261 #define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority
262 #define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority
263 #define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority
264 #define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority
265 #define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority
266 #define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority
270 * The following are defines for the bit fields in the ADC_O_SPC register.
273 #define ADC_SPC_PHASE_M 0x0000000F ///< Phase Difference
274 #define ADC_SPC_PHASE_0 0x00000000 ///< ADC sample lags by 0.0
275 #define ADC_SPC_PHASE_22_5 0x00000001 ///< ADC sample lags by 22.5
276 #define ADC_SPC_PHASE_45 0x00000002 ///< ADC sample lags by 45.0
277 #define ADC_SPC_PHASE_67_5 0x00000003 ///< ADC sample lags by 67.5
278 #define ADC_SPC_PHASE_90 0x00000004 ///< ADC sample lags by 90.0
279 #define ADC_SPC_PHASE_112_5 0x00000005 ///< ADC sample lags by 112.5
280 #define ADC_SPC_PHASE_135 0x00000006 ///< ADC sample lags by 135.0
281 #define ADC_SPC_PHASE_157_5 0x00000007 ///< ADC sample lags by 157.5
282 #define ADC_SPC_PHASE_180 0x00000008 ///< ADC sample lags by 180.0
283 #define ADC_SPC_PHASE_202_5 0x00000009 ///< ADC sample lags by 202.5
284 #define ADC_SPC_PHASE_225 0x0000000A ///< ADC sample lags by 225.0
285 #define ADC_SPC_PHASE_247_5 0x0000000B ///< ADC sample lags by 247.5
286 #define ADC_SPC_PHASE_270 0x0000000C ///< ADC sample lags by 270.0
287 #define ADC_SPC_PHASE_292_5 0x0000000D ///< ADC sample lags by 292.5
288 #define ADC_SPC_PHASE_315 0x0000000E ///< ADC sample lags by 315.0
289 #define ADC_SPC_PHASE_337_5 0x0000000F ///< ADC sample lags by 337.5
293 * The following are defines for the bit fields in the ADC_O_PSSI register.
295 #define ADC_PSSI_GSYNC 0x80000000 ///< Global Synchronize
296 #define ADC_PSSI_SYNCWAIT 0x08000000 ///< Synchronize Wait
297 #define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate
298 #define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate
299 #define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate
300 #define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate
304 * The following are defines for the bit fields in the ADC_O_SAC register.
306 #define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control
307 #define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling
308 #define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling
309 #define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling
310 #define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling
311 #define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling
312 #define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling
313 #define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling
317 * The following are defines for the bit fields in the ADC_O_DCISC register.
319 #define ADC_DCISC_DCINT7 0x00000080 ///< Digital Comparator 7 Interrupt
320 ///< Status and Clear
321 #define ADC_DCISC_DCINT6 0x00000040 ///< Digital Comparator 6 Interrupt
322 ///< Status and Clear
323 #define ADC_DCISC_DCINT5 0x00000020 ///< Digital Comparator 5 Interrupt
324 ///< Status and Clear
325 #define ADC_DCISC_DCINT4 0x00000010 ///< Digital Comparator 4 Interrupt
326 ///< Status and Clear
327 #define ADC_DCISC_DCINT3 0x00000008 ///< Digital Comparator 3 Interrupt
328 ///< Status and Clear
329 #define ADC_DCISC_DCINT2 0x00000004 ///< Digital Comparator 2 Interrupt
330 ///< Status and Clear
331 #define ADC_DCISC_DCINT1 0x00000002 ///< Digital Comparator 1 Interrupt
332 ///< Status and Clear
333 #define ADC_DCISC_DCINT0 0x00000001 ///< Digital Comparator 0 Interrupt
334 ///< Status and Clear
338 * The following are defines for the bit fields in the ADC_O_CTL register.
340 #define ADC_CTL_VREF 0x00000001 ///< Voltage Reference Select
345 * The following are defines for the bit fields in the ADC_O_ACTSS register.
348 #define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable
349 #define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable
350 #define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable
351 #define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable
355 * The following are defines for the bit fields in the ADC_O_RIS register.
358 #define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status
359 #define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status
360 #define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status
361 #define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status
365 * The following are defines for the bit fields in the ADC_O_IM register.
368 #define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask
369 #define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask
370 #define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask
371 #define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask
375 * The following are defines for the bit fields in the ADC_O_ISC register.
378 #define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear
379 #define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear
380 #define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear
381 #define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear
385 * The following are defines for the bit fields in the ADC_O_OSTAT register.
388 #define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow
389 #define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow
390 #define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow
391 #define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow
395 * The following are defines for the bit fields in the ADC_O_EMUX register.
398 #define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select
399 #define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default)
400 #define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0
401 #define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1
402 #define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2
403 #define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4)
404 #define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer
405 #define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0
406 #define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1
407 #define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2
408 #define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample)
409 #define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select
410 #define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default)
411 #define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0
412 #define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1
413 #define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2
414 #define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4)
415 #define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer
416 #define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0
417 #define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1
418 #define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2
419 #define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample)
420 #define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select
421 #define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default)
422 #define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0
423 #define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1
424 #define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2
425 #define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4)
426 #define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer
427 #define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0
428 #define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1
429 #define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2
430 #define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample)
431 #define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select
432 #define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default)
433 #define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0
434 #define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1
435 #define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2
436 #define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4)
437 #define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer
438 #define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0
439 #define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1
440 #define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2
441 #define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample)
445 * The following are defines for the bit fields in the ADC_O_USTAT register.
448 #define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow
449 #define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow
450 #define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow
451 #define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow
455 * The following are defines for the bit fields in the ADC_O_SSPRI register.
458 #define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority
459 #define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority
460 #define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority
461 #define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority
462 #define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority
463 #define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority
464 #define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority
465 #define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority
466 #define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority
467 #define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority
468 #define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority
469 #define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority
470 #define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority
471 #define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority
472 #define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority
473 #define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority
474 #define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority
475 #define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority
476 #define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority
477 #define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority
481 * The following are defines for the bit fields in the ADC_O_PSSI register.
484 #define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate
485 #define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate
486 #define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate
487 #define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate
491 * The following are defines for the bit fields in the ADC_O_SAC register.
494 #define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control
495 #define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling
496 #define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling
497 #define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling
498 #define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling
499 #define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling
500 #define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling
501 #define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling
505 * The following are defines for the bit fields in the ADC_O_SSMUX0 register.
508 #define ADC_SSMUX0_MUX7_M 0x70000000 ///< 8th Sample Input Select
509 #define ADC_SSMUX0_MUX6_M 0x07000000 ///< 7th Sample Input Select
510 #define ADC_SSMUX0_MUX5_M 0x00700000 ///< 6th Sample Input Select
511 #define ADC_SSMUX0_MUX4_M 0x00070000 ///< 5th Sample Input Select
512 #define ADC_SSMUX0_MUX3_M 0x00007000 ///< 4th Sample Input Select
513 #define ADC_SSMUX0_MUX2_M 0x00000700 ///< 3rd Sample Input Select
514 #define ADC_SSMUX0_MUX1_M 0x00000070 ///< 2nd Sample Input Select
515 #define ADC_SSMUX0_MUX0_M 0x00000007 ///< 1st Sample Input Select
516 #define ADC_SSMUX0_MUX7_S 28
517 #define ADC_SSMUX0_MUX6_S 24
518 #define ADC_SSMUX0_MUX5_S 20
519 #define ADC_SSMUX0_MUX4_S 16
520 #define ADC_SSMUX0_MUX3_S 12
521 #define ADC_SSMUX0_MUX2_S 8
522 #define ADC_SSMUX0_MUX1_S 4
523 #define ADC_SSMUX0_MUX0_S 0
527 * The following are defines for the bit fields in the ADC_O_SSCTL0 register.
530 #define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select
531 #define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable
532 #define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence
533 #define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select
534 #define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select
535 #define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable
536 #define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence
537 #define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select
538 #define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select
539 #define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable
540 #define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence
541 #define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select
542 #define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select
543 #define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable
544 #define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence
545 #define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select
546 #define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
547 #define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable
548 #define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence
549 #define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select
550 #define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
551 #define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
552 #define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence
553 #define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select
554 #define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
555 #define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
556 #define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence
557 #define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select
558 #define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
559 #define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable
560 #define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence
561 #define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select
565 * The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
568 #define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data
569 #define ADC_SSFIFO0_DATA_S 0
573 * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
576 #define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full
577 #define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty
578 #define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer
579 #define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer
580 #define ADC_SSFSTAT0_HPTR_S 4
581 #define ADC_SSFSTAT0_TPTR_S 0
585 * The following are defines for the bit fields in the ADC_O_SSMUX1 register.
588 #define ADC_SSMUX1_MUX3_M 0x00007000 ///< 4th Sample Input Select
589 #define ADC_SSMUX1_MUX2_M 0x00000700 ///< 3rd Sample Input Select
590 #define ADC_SSMUX1_MUX1_M 0x00000070 ///< 2nd Sample Input Select
591 #define ADC_SSMUX1_MUX0_M 0x00000007 ///< 1st Sample Input Select
592 #define ADC_SSMUX1_MUX3_S 12
593 #define ADC_SSMUX1_MUX2_S 8
594 #define ADC_SSMUX1_MUX1_S 4
595 #define ADC_SSMUX1_MUX0_S 0
599 * The following are defines for the bit fields in the ADC_O_SSCTL1 register.
602 #define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
603 #define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable
604 #define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence
605 #define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select
606 #define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
607 #define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
608 #define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence
609 #define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select
610 #define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
611 #define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
612 #define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence
613 #define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select
614 #define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
615 #define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable
616 #define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence
617 #define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select
621 * The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
624 #define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data
625 #define ADC_SSFIFO1_DATA_S 0
629 * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
632 #define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full
633 #define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty
634 #define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer
635 #define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer
636 #define ADC_SSFSTAT1_HPTR_S 4
637 #define ADC_SSFSTAT1_TPTR_S 0
642 * The following are defines for the bit fields in the ADC_O_SSCTL2 register.
645 #define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
646 #define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable
647 #define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence
648 #define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select
649 #define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
650 #define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
651 #define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence
652 #define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select
653 #define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
654 #define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
655 #define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence
656 #define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select
657 #define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
658 #define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable
659 #define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence
660 #define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select
664 * The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
667 #define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data
668 #define ADC_SSFIFO2_DATA_S 0
672 * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
675 #define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full
676 #define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty
677 #define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer
678 #define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer
679 #define ADC_SSFSTAT2_HPTR_S 4
680 #define ADC_SSFSTAT2_TPTR_S 0
684 * The following are defines for the bit fields in the ADC_O_SSCTL3 register.
687 #define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
688 #define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable
689 #define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence
690 #define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select
694 * The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
697 #define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data
698 #define ADC_SSFIFO3_DATA_S 0
702 * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
705 #define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full
706 #define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty
707 #define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer
708 #define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer
709 #define ADC_SSFSTAT3_HPTR_S 4
710 #define ADC_SSFSTAT3_TPTR_S 0
714 * The following are defines for the bit fields in the ADC_O_TMLB register.
717 #define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable
721 * The following are defines for the the interpretation of the data in the
722 * SSFIFOx when the ADC TMLB is enabled.
725 #define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
726 #define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
727 #define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
728 #define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
729 #define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
730 #define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift
731 #define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift
736 * The following are defines for the bit fields in the ADC_O_SSMUX0 register.
738 #define ADC_SSMUX0_MUX7_S 28
739 #define ADC_SSMUX0_MUX6_S 24
740 #define ADC_SSMUX0_MUX5_S 20
741 #define ADC_SSMUX0_MUX4_S 16
742 #define ADC_SSMUX0_MUX3_S 12
743 #define ADC_SSMUX0_MUX2_S 8
744 #define ADC_SSMUX0_MUX1_S 4
745 #define ADC_SSMUX0_MUX0_S 0
749 * The following are defines for the bit fields in the ADC_O_SSCTL0 register.
751 #define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select
752 #define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable
753 #define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence
754 #define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select
755 #define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select
756 #define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable
757 #define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence
758 #define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select
759 #define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select
760 #define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable
761 #define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence
762 #define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select
763 #define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select
764 #define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable
765 #define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence
766 #define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select
767 #define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
768 #define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable
769 #define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence
770 #define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select
771 #define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
772 #define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
773 #define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence
774 #define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select
775 #define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
776 #define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
777 #define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence
778 #define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select
779 #define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
780 #define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable
781 #define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence
782 #define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select
786 * The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
788 #define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data
789 #define ADC_SSFIFO0_DATA_S 0
793 * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
795 #define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full
796 #define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty
797 #define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer
798 #define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer
799 #define ADC_SSFSTAT0_HPTR_S 4
800 #define ADC_SSFSTAT0_TPTR_S 0
804 * The following are defines for the bit fields in the ADC_O_SSOP0 register.
806 #define ADC_SSOP0_S7DCOP 0x10000000 ///< Sample 7 Digital Comparator
808 #define ADC_SSOP0_S6DCOP 0x01000000 ///< Sample 6 Digital Comparator
810 #define ADC_SSOP0_S5DCOP 0x00100000 ///< Sample 5 Digital Comparator
812 #define ADC_SSOP0_S4DCOP 0x00010000 ///< Sample 4 Digital Comparator
814 #define ADC_SSOP0_S3DCOP 0x00001000 ///< Sample 3 Digital Comparator
816 #define ADC_SSOP0_S2DCOP 0x00000100 ///< Sample 2 Digital Comparator
818 #define ADC_SSOP0_S1DCOP 0x00000010 ///< Sample 1 Digital Comparator
820 #define ADC_SSOP0_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator
825 * The following are defines for the bit fields in the ADC_O_SSDC0 register.
827 #define ADC_SSDC0_S7DCSEL_M 0xF0000000 ///< Sample 7 Digital Comparator
829 #define ADC_SSDC0_S6DCSEL_M 0x0F000000 ///< Sample 6 Digital Comparator
831 #define ADC_SSDC0_S5DCSEL_M 0x00F00000 ///< Sample 5 Digital Comparator
833 #define ADC_SSDC0_S4DCSEL_M 0x000F0000 ///< Sample 4 Digital Comparator
835 #define ADC_SSDC0_S3DCSEL_M 0x0000F000 ///< Sample 3 Digital Comparator
837 #define ADC_SSDC0_S2DCSEL_M 0x00000F00 ///< Sample 2 Digital Comparator
839 #define ADC_SSDC0_S1DCSEL_M 0x000000F0 ///< Sample 1 Digital Comparator
841 #define ADC_SSDC0_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator
843 #define ADC_SSDC0_S6DCSEL_S 24
844 #define ADC_SSDC0_S5DCSEL_S 20
845 #define ADC_SSDC0_S4DCSEL_S 16
846 #define ADC_SSDC0_S3DCSEL_S 12
847 #define ADC_SSDC0_S2DCSEL_S 8
848 #define ADC_SSDC0_S1DCSEL_S 4
849 #define ADC_SSDC0_S0DCSEL_S 0
853 * The following are defines for the bit fields in the ADC_O_SSCTL1 register.
855 #define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
856 #define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable
857 #define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence
858 #define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select
859 #define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
860 #define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
861 #define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence
862 #define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select
863 #define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
864 #define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
865 #define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence
866 #define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select
867 #define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
868 #define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable
869 #define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence
870 #define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select
874 * The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
876 #define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data
877 #define ADC_SSFIFO1_DATA_S 0
881 * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
883 #define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full
884 #define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty
885 #define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer
886 #define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer
887 #define ADC_SSFSTAT1_HPTR_S 4
888 #define ADC_SSFSTAT1_TPTR_S 0
892 * The following are defines for the bit fields in the ADC_O_SSOP1 register.
894 #define ADC_SSOP1_S3DCOP 0x00001000 ///< Sample 3 Digital Comparator
896 #define ADC_SSOP1_S2DCOP 0x00000100 ///< Sample 2 Digital Comparator
898 #define ADC_SSOP1_S1DCOP 0x00000010 ///< Sample 1 Digital Comparator
900 #define ADC_SSOP1_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator
905 * The following are defines for the bit fields in the ADC_O_SSDC1 register.
907 #define ADC_SSDC1_S3DCSEL_M 0x0000F000 ///< Sample 3 Digital Comparator
909 #define ADC_SSDC1_S2DCSEL_M 0x00000F00 ///< Sample 2 Digital Comparator
911 #define ADC_SSDC1_S1DCSEL_M 0x000000F0 ///< Sample 1 Digital Comparator
913 #define ADC_SSDC1_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator
915 #define ADC_SSDC1_S2DCSEL_S 8
916 #define ADC_SSDC1_S1DCSEL_S 4
917 #define ADC_SSDC1_S0DCSEL_S 0
921 * The following are defines for the bit fields in the ADC_O_SSMUX2 register.
923 #define ADC_SSMUX2_MUX3_M 0x0000F000 ///< 4th Sample Input Select
924 #define ADC_SSMUX2_MUX2_M 0x00000F00 ///< 3rd Sample Input Select
925 #define ADC_SSMUX2_MUX1_M 0x000000F0 ///< 2nd Sample Input Select
926 #define ADC_SSMUX2_MUX0_M 0x0000000F ///< 1st Sample Input Select
927 #define ADC_SSMUX2_MUX3_S 12
928 #define ADC_SSMUX2_MUX2_S 8
929 #define ADC_SSMUX2_MUX1_S 4
930 #define ADC_SSMUX2_MUX0_S 0
934 * The following are defines for the bit fields in the ADC_O_SSCTL2 register.
936 #define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
937 #define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable
938 #define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence
939 #define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select
940 #define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
941 #define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
942 #define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence
943 #define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select
944 #define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
945 #define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
946 #define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence
947 #define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select
948 #define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
949 #define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable
950 #define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence
951 #define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select
955 * The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
957 #define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data
958 #define ADC_SSFIFO2_DATA_S 0
962 * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
964 #define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full
965 #define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty
966 #define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer
967 #define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer
968 #define ADC_SSFSTAT2_HPTR_S 4
969 #define ADC_SSFSTAT2_TPTR_S 0
973 * The following are defines for the bit fields in the ADC_O_SSOP2 register.
975 #define ADC_SSOP2_S3DCOP 0x00001000 ///< Sample 3 Digital Comparator
977 #define ADC_SSOP2_S2DCOP 0x00000100 ///< Sample 2 Digital Comparator
979 #define ADC_SSOP2_S1DCOP 0x00000010 ///< Sample 1 Digital Comparator
981 #define ADC_SSOP2_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator
986 * The following are defines for the bit fields in the ADC_O_SSDC2 register.
988 #define ADC_SSDC2_S3DCSEL_M 0x0000F000 ///< Sample 3 Digital Comparator
990 #define ADC_SSDC2_S2DCSEL_M 0x00000F00 ///< Sample 2 Digital Comparator
992 #define ADC_SSDC2_S1DCSEL_M 0x000000F0 ///< Sample 1 Digital Comparator
994 #define ADC_SSDC2_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator
996 #define ADC_SSDC2_S2DCSEL_S 8
997 #define ADC_SSDC2_S1DCSEL_S 4
998 #define ADC_SSDC2_S0DCSEL_S 0
1002 * The following are defines for the bit fields in the ADC_O_SSMUX3 register.
1004 #define ADC_SSMUX3_MUX0_M 0x0000000F ///< 1st Sample Input Select
1005 #define ADC_SSMUX3_MUX0_S 0
1009 * The following are defines for the bit fields in the ADC_O_SSCTL3 register.
1011 #define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
1012 #define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable
1013 #define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence
1014 #define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select
1018 * The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
1020 #define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data
1021 #define ADC_SSFIFO3_DATA_S 0
1025 * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
1027 #define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full
1028 #define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty
1029 #define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer
1030 #define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer
1031 #define ADC_SSFSTAT3_HPTR_S 4
1032 #define ADC_SSFSTAT3_TPTR_S 0
1036 * The following are defines for the bit fields in the ADC_O_SSOP3 register.
1038 #define ADC_SSOP3_S0DCOP 0x00000001 ///< Sample 0 Digital Comparator
1043 * The following are defines for the bit fields in the ADC_O_SSDC3 register.
1045 #define ADC_SSDC3_S0DCSEL_M 0x0000000F ///< Sample 0 Digital Comparator
1050 * The following are defines for the bit fields in the ADC_O_TMLB register.
1052 #define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable
1056 * The following are defines for the bit fields in the ADC_O_DCRIC register.
1058 #define ADC_DCRIC_DCTRIG7 0x00800000 ///< Digital Comparator Trigger 7
1059 #define ADC_DCRIC_DCTRIG6 0x00400000 ///< Digital Comparator Trigger 6
1060 #define ADC_DCRIC_DCTRIG5 0x00200000 ///< Digital Comparator Trigger 5
1061 #define ADC_DCRIC_DCTRIG4 0x00100000 ///< Digital Comparator Trigger 4
1062 #define ADC_DCRIC_DCTRIG3 0x00080000 ///< Digital Comparator Trigger 3
1063 #define ADC_DCRIC_DCTRIG2 0x00040000 ///< Digital Comparator Trigger 2
1064 #define ADC_DCRIC_DCTRIG1 0x00020000 ///< Digital Comparator Trigger 1
1065 #define ADC_DCRIC_DCTRIG0 0x00010000 ///< Digital Comparator Trigger 0
1066 #define ADC_DCRIC_DCINT7 0x00000080 ///< Digital Comparator Interrupt 7
1067 #define ADC_DCRIC_DCINT6 0x00000040 ///< Digital Comparator Interrupt 6
1068 #define ADC_DCRIC_DCINT5 0x00000020 ///< Digital Comparator Interrupt 5
1069 #define ADC_DCRIC_DCINT4 0x00000010 ///< Digital Comparator Interrupt 4
1070 #define ADC_DCRIC_DCINT3 0x00000008 ///< Digital Comparator Interrupt 3
1071 #define ADC_DCRIC_DCINT2 0x00000004 ///< Digital Comparator Interrupt 2
1072 #define ADC_DCRIC_DCINT1 0x00000002 ///< Digital Comparator Interrupt 1
1073 #define ADC_DCRIC_DCINT0 0x00000001 ///< Digital Comparator Interrupt 0
1077 * The following are defines for the bit fields in the ADC_O_DCCTL0 register.
1079 #define ADC_DCCTL0_CTE 0x00001000 ///< Comparison Trigger Enable
1080 #define ADC_DCCTL0_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1081 #define ADC_DCCTL0_CTC_LOW 0x00000000 ///< Low Band
1082 #define ADC_DCCTL0_CTC_MID 0x00000400 ///< Mid Band
1083 #define ADC_DCCTL0_CTC_HIGH 0x00000C00 ///< High Band
1084 #define ADC_DCCTL0_CTM_M 0x00000300 ///< Comparison Trigger Mode
1085 #define ADC_DCCTL0_CTM_ALWAYS 0x00000000 ///< Always
1086 #define ADC_DCCTL0_CTM_ONCE 0x00000100 ///< Once
1087 #define ADC_DCCTL0_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1088 #define ADC_DCCTL0_CTM_HONCE 0x00000300 ///< Hysteresis Once
1089 #define ADC_DCCTL0_CIE 0x00000010 ///< Comparison Interrupt Enable
1090 #define ADC_DCCTL0_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1091 #define ADC_DCCTL0_CIC_LOW 0x00000000 ///< Low Band
1092 #define ADC_DCCTL0_CIC_MID 0x00000004 ///< Mid Band
1093 #define ADC_DCCTL0_CIC_HIGH 0x0000000C ///< High Band
1094 #define ADC_DCCTL0_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1095 #define ADC_DCCTL0_CIM_ALWAYS 0x00000000 ///< Always
1096 #define ADC_DCCTL0_CIM_ONCE 0x00000001 ///< Once
1097 #define ADC_DCCTL0_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1098 #define ADC_DCCTL0_CIM_HONCE 0x00000003 ///< Hysteresis Once
1102 * The following are defines for the bit fields in the ADC_O_DCCTL1 register.
1104 #define ADC_DCCTL1_CTE 0x00001000 ///< Comparison Trigger Enable
1105 #define ADC_DCCTL1_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1106 #define ADC_DCCTL1_CTC_LOW 0x00000000 ///< Low Band
1107 #define ADC_DCCTL1_CTC_MID 0x00000400 ///< Mid Band
1108 #define ADC_DCCTL1_CTC_HIGH 0x00000C00 ///< High Band
1109 #define ADC_DCCTL1_CTM_M 0x00000300 ///< Comparison Trigger Mode
1110 #define ADC_DCCTL1_CTM_ALWAYS 0x00000000 ///< Always
1111 #define ADC_DCCTL1_CTM_ONCE 0x00000100 ///< Once
1112 #define ADC_DCCTL1_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1113 #define ADC_DCCTL1_CTM_HONCE 0x00000300 ///< Hysteresis Once
1114 #define ADC_DCCTL1_CIE 0x00000010 ///< Comparison Interrupt Enable
1115 #define ADC_DCCTL1_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1116 #define ADC_DCCTL1_CIC_LOW 0x00000000 ///< Low Band
1117 #define ADC_DCCTL1_CIC_MID 0x00000004 ///< Mid Band
1118 #define ADC_DCCTL1_CIC_HIGH 0x0000000C ///< High Band
1119 #define ADC_DCCTL1_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1120 #define ADC_DCCTL1_CIM_ALWAYS 0x00000000 ///< Always
1121 #define ADC_DCCTL1_CIM_ONCE 0x00000001 ///< Once
1122 #define ADC_DCCTL1_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1123 #define ADC_DCCTL1_CIM_HONCE 0x00000003 ///< Hysteresis Once
1127 * The following are defines for the bit fields in the ADC_O_DCCTL2 register.
1129 #define ADC_DCCTL2_CTE 0x00001000 ///< Comparison Trigger Enable
1130 #define ADC_DCCTL2_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1131 #define ADC_DCCTL2_CTC_LOW 0x00000000 ///< Low Band
1132 #define ADC_DCCTL2_CTC_MID 0x00000400 ///< Mid Band
1133 #define ADC_DCCTL2_CTC_HIGH 0x00000C00 ///< High Band
1134 #define ADC_DCCTL2_CTM_M 0x00000300 ///< Comparison Trigger Mode
1135 #define ADC_DCCTL2_CTM_ALWAYS 0x00000000 ///< Always
1136 #define ADC_DCCTL2_CTM_ONCE 0x00000100 ///< Once
1137 #define ADC_DCCTL2_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1138 #define ADC_DCCTL2_CTM_HONCE 0x00000300 ///< Hysteresis Once
1139 #define ADC_DCCTL2_CIE 0x00000010 ///< Comparison Interrupt Enable
1140 #define ADC_DCCTL2_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1141 #define ADC_DCCTL2_CIC_LOW 0x00000000 ///< Low Band
1142 #define ADC_DCCTL2_CIC_MID 0x00000004 ///< Mid Band
1143 #define ADC_DCCTL2_CIC_HIGH 0x0000000C ///< High Band
1144 #define ADC_DCCTL2_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1145 #define ADC_DCCTL2_CIM_ALWAYS 0x00000000 ///< Always
1146 #define ADC_DCCTL2_CIM_ONCE 0x00000001 ///< Once
1147 #define ADC_DCCTL2_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1148 #define ADC_DCCTL2_CIM_HONCE 0x00000003 ///< Hysteresis Once
1152 * The following are defines for the bit fields in the ADC_O_DCCTL3 register.
1154 #define ADC_DCCTL3_CTE 0x00001000 ///< Comparison Trigger Enable
1155 #define ADC_DCCTL3_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1156 #define ADC_DCCTL3_CTC_LOW 0x00000000 ///< Low Band
1157 #define ADC_DCCTL3_CTC_MID 0x00000400 ///< Mid Band
1158 #define ADC_DCCTL3_CTC_HIGH 0x00000C00 ///< High Band
1159 #define ADC_DCCTL3_CTM_M 0x00000300 ///< Comparison Trigger Mode
1160 #define ADC_DCCTL3_CTM_ALWAYS 0x00000000 ///< Always
1161 #define ADC_DCCTL3_CTM_ONCE 0x00000100 ///< Once
1162 #define ADC_DCCTL3_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1163 #define ADC_DCCTL3_CTM_HONCE 0x00000300 ///< Hysteresis Once
1164 #define ADC_DCCTL3_CIE 0x00000010 ///< Comparison Interrupt Enable
1165 #define ADC_DCCTL3_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1166 #define ADC_DCCTL3_CIC_LOW 0x00000000 ///< Low Band
1167 #define ADC_DCCTL3_CIC_MID 0x00000004 ///< Mid Band
1168 #define ADC_DCCTL3_CIC_HIGH 0x0000000C ///< High Band
1169 #define ADC_DCCTL3_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1170 #define ADC_DCCTL3_CIM_ALWAYS 0x00000000 ///< Always
1171 #define ADC_DCCTL3_CIM_ONCE 0x00000001 ///< Once
1172 #define ADC_DCCTL3_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1173 #define ADC_DCCTL3_CIM_HONCE 0x00000003 ///< Hysteresis Once
1177 * The following are defines for the bit fields in the ADC_O_DCCTL4 register.
1179 #define ADC_DCCTL4_CTE 0x00001000 ///< Comparison Trigger Enable
1180 #define ADC_DCCTL4_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1181 #define ADC_DCCTL4_CTC_LOW 0x00000000 ///< Low Band
1182 #define ADC_DCCTL4_CTC_MID 0x00000400 ///< Mid Band
1183 #define ADC_DCCTL4_CTC_HIGH 0x00000C00 ///< High Band
1184 #define ADC_DCCTL4_CTM_M 0x00000300 ///< Comparison Trigger Mode
1185 #define ADC_DCCTL4_CTM_ALWAYS 0x00000000 ///< Always
1186 #define ADC_DCCTL4_CTM_ONCE 0x00000100 ///< Once
1187 #define ADC_DCCTL4_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1188 #define ADC_DCCTL4_CTM_HONCE 0x00000300 ///< Hysteresis Once
1189 #define ADC_DCCTL4_CIE 0x00000010 ///< Comparison Interrupt Enable
1190 #define ADC_DCCTL4_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1191 #define ADC_DCCTL4_CIC_LOW 0x00000000 ///< Low Band
1192 #define ADC_DCCTL4_CIC_MID 0x00000004 ///< Mid Band
1193 #define ADC_DCCTL4_CIC_HIGH 0x0000000C ///< High Band
1194 #define ADC_DCCTL4_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1195 #define ADC_DCCTL4_CIM_ALWAYS 0x00000000 ///< Always
1196 #define ADC_DCCTL4_CIM_ONCE 0x00000001 ///< Once
1197 #define ADC_DCCTL4_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1198 #define ADC_DCCTL4_CIM_HONCE 0x00000003 ///< Hysteresis Once
1202 * The following are defines for the bit fields in the ADC_O_DCCTL5 register.
1204 #define ADC_DCCTL5_CTE 0x00001000 ///< Comparison Trigger Enable
1205 #define ADC_DCCTL5_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1206 #define ADC_DCCTL5_CTC_LOW 0x00000000 ///< Low Band
1207 #define ADC_DCCTL5_CTC_MID 0x00000400 ///< Mid Band
1208 #define ADC_DCCTL5_CTC_HIGH 0x00000C00 ///< High Band
1209 #define ADC_DCCTL5_CTM_M 0x00000300 ///< Comparison Trigger Mode
1210 #define ADC_DCCTL5_CTM_ALWAYS 0x00000000 ///< Always
1211 #define ADC_DCCTL5_CTM_ONCE 0x00000100 ///< Once
1212 #define ADC_DCCTL5_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1213 #define ADC_DCCTL5_CTM_HONCE 0x00000300 ///< Hysteresis Once
1214 #define ADC_DCCTL5_CIE 0x00000010 ///< Comparison Interrupt Enable
1215 #define ADC_DCCTL5_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1216 #define ADC_DCCTL5_CIC_LOW 0x00000000 ///< Low Band
1217 #define ADC_DCCTL5_CIC_MID 0x00000004 ///< Mid Band
1218 #define ADC_DCCTL5_CIC_HIGH 0x0000000C ///< High Band
1219 #define ADC_DCCTL5_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1220 #define ADC_DCCTL5_CIM_ALWAYS 0x00000000 ///< Always
1221 #define ADC_DCCTL5_CIM_ONCE 0x00000001 ///< Once
1222 #define ADC_DCCTL5_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1223 #define ADC_DCCTL5_CIM_HONCE 0x00000003 ///< Hysteresis Once
1227 * The following are defines for the bit fields in the ADC_O_DCCTL6 register.
1229 #define ADC_DCCTL6_CTE 0x00001000 ///< Comparison Trigger Enable
1230 #define ADC_DCCTL6_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1231 #define ADC_DCCTL6_CTC_LOW 0x00000000 ///< Low Band
1232 #define ADC_DCCTL6_CTC_MID 0x00000400 ///< Mid Band
1233 #define ADC_DCCTL6_CTC_HIGH 0x00000C00 ///< High Band
1234 #define ADC_DCCTL6_CTM_M 0x00000300 ///< Comparison Trigger Mode
1235 #define ADC_DCCTL6_CTM_ALWAYS 0x00000000 ///< Always
1236 #define ADC_DCCTL6_CTM_ONCE 0x00000100 ///< Once
1237 #define ADC_DCCTL6_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1238 #define ADC_DCCTL6_CTM_HONCE 0x00000300 ///< Hysteresis Once
1239 #define ADC_DCCTL6_CIE 0x00000010 ///< Comparison Interrupt Enable
1240 #define ADC_DCCTL6_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1241 #define ADC_DCCTL6_CIC_LOW 0x00000000 ///< Low Band
1242 #define ADC_DCCTL6_CIC_MID 0x00000004 ///< Mid Band
1243 #define ADC_DCCTL6_CIC_HIGH 0x0000000C ///< High Band
1244 #define ADC_DCCTL6_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1245 #define ADC_DCCTL6_CIM_ALWAYS 0x00000000 ///< Always
1246 #define ADC_DCCTL6_CIM_ONCE 0x00000001 ///< Once
1247 #define ADC_DCCTL6_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1248 #define ADC_DCCTL6_CIM_HONCE 0x00000003 ///< Hysteresis Once
1252 * The following are defines for the bit fields in the ADC_O_DCCTL7 register.
1254 #define ADC_DCCTL7_CTE 0x00001000 ///< Comparison Trigger Enable
1255 #define ADC_DCCTL7_CTC_M 0x00000C00 ///< Comparison Trigger Condition
1256 #define ADC_DCCTL7_CTC_LOW 0x00000000 ///< Low Band
1257 #define ADC_DCCTL7_CTC_MID 0x00000400 ///< Mid Band
1258 #define ADC_DCCTL7_CTC_HIGH 0x00000C00 ///< High Band
1259 #define ADC_DCCTL7_CTM_M 0x00000300 ///< Comparison Trigger Mode
1260 #define ADC_DCCTL7_CTM_ALWAYS 0x00000000 ///< Always
1261 #define ADC_DCCTL7_CTM_ONCE 0x00000100 ///< Once
1262 #define ADC_DCCTL7_CTM_HALWAYS 0x00000200 ///< Hysteresis Always
1263 #define ADC_DCCTL7_CTM_HONCE 0x00000300 ///< Hysteresis Once
1264 #define ADC_DCCTL7_CIE 0x00000010 ///< Comparison Interrupt Enable
1265 #define ADC_DCCTL7_CIC_M 0x0000000C ///< Comparison Interrupt Condition
1266 #define ADC_DCCTL7_CIC_LOW 0x00000000 ///< Low Band
1267 #define ADC_DCCTL7_CIC_MID 0x00000004 ///< Mid Band
1268 #define ADC_DCCTL7_CIC_HIGH 0x0000000C ///< High Band
1269 #define ADC_DCCTL7_CIM_M 0x00000003 ///< Comparison Interrupt Mode
1270 #define ADC_DCCTL7_CIM_ALWAYS 0x00000000 ///< Always
1271 #define ADC_DCCTL7_CIM_ONCE 0x00000001 ///< Once
1272 #define ADC_DCCTL7_CIM_HALWAYS 0x00000002 ///< Hysteresis Always
1273 #define ADC_DCCTL7_CIM_HONCE 0x00000003 ///< Hysteresis Once
1277 * The following are defines for the bit fields in the ADC_O_DCCMP0 register.
1279 #define ADC_DCCMP0_COMP1_M 0x03FF0000 ///< Compare 1
1280 #define ADC_DCCMP0_COMP0_M 0x000003FF ///< Compare 0
1281 #define ADC_DCCMP0_COMP1_S 16
1282 #define ADC_DCCMP0_COMP0_S 0
1286 * The following are defines for the bit fields in the ADC_O_DCCMP1 register.
1288 #define ADC_DCCMP1_COMP1_M 0x03FF0000 ///< Compare 1
1289 #define ADC_DCCMP1_COMP0_M 0x000003FF ///< Compare 0
1290 #define ADC_DCCMP1_COMP1_S 16
1291 #define ADC_DCCMP1_COMP0_S 0
1295 * The following are defines for the bit fields in the ADC_O_DCCMP2 register.
1297 #define ADC_DCCMP2_COMP1_M 0x03FF0000 ///< Compare 1
1298 #define ADC_DCCMP2_COMP0_M 0x000003FF ///< Compare 0
1299 #define ADC_DCCMP2_COMP1_S 16
1300 #define ADC_DCCMP2_COMP0_S 0
1304 * The following are defines for the bit fields in the ADC_O_DCCMP3 register.
1306 #define ADC_DCCMP3_COMP1_M 0x03FF0000 ///< Compare 1
1307 #define ADC_DCCMP3_COMP0_M 0x000003FF ///< Compare 0
1308 #define ADC_DCCMP3_COMP1_S 16
1309 #define ADC_DCCMP3_COMP0_S 0
1313 * The following are defines for the bit fields in the ADC_O_DCCMP4 register.
1315 #define ADC_DCCMP4_COMP1_M 0x03FF0000 ///< Compare 1
1316 #define ADC_DCCMP4_COMP0_M 0x000003FF ///< Compare 0
1317 #define ADC_DCCMP4_COMP1_S 16
1318 #define ADC_DCCMP4_COMP0_S 0
1322 * The following are defines for the bit fields in the ADC_O_DCCMP5 register.
1324 #define ADC_DCCMP5_COMP1_M 0x03FF0000 ///< Compare 1
1325 #define ADC_DCCMP5_COMP0_M 0x000003FF ///< Compare 0
1326 #define ADC_DCCMP5_COMP1_S 16
1327 #define ADC_DCCMP5_COMP0_S 0
1331 * The following are defines for the bit fields in the ADC_O_DCCMP6 register.
1333 #define ADC_DCCMP6_COMP1_M 0x03FF0000 ///< Compare 1
1334 #define ADC_DCCMP6_COMP0_M 0x000003FF ///< Compare 0
1335 #define ADC_DCCMP6_COMP1_S 16
1336 #define ADC_DCCMP6_COMP0_S 0
1340 * The following are defines for the bit fields in the ADC_O_DCCMP7 register.
1342 #define ADC_DCCMP7_COMP1_M 0x03FF0000 ///< Compare 1
1343 #define ADC_DCCMP7_COMP0_M 0x000003FF ///< Compare 0
1344 #define ADC_DCCMP7_COMP1_S 16
1345 #define ADC_DCCMP7_COMP0_S 0
1349 * The following are defines for the the interpretation of the data in the
1350 * SSFIFOx when the ADC TMLB is enabled.
1353 #define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
1354 #define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
1355 #define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
1356 #define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
1357 #define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
1358 #define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift
1359 #define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift
1361 #endif /* LM3S_ADC_H */