4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 interrupts definition.
40 * The following are defines for the fault assignments.
43 #define FAULT_NMI 2 ///< NMI fault
44 #define FAULT_HARD 3 ///< Hard fault
45 #define FAULT_MPU 4 ///< MPU fault
46 #define FAULT_BUS 5 ///< Bus fault
47 #define FAULT_USAGE 6 ///< Usage fault
48 #define FAULT_SVCALL 11 ///< SVCall
49 #define FAULT_DEBUG 12 ///< Debug monitor
50 #define FAULT_PENDSV 14 ///< PendSV
51 #define FAULT_SYSTICK 15 ///< System Tick
55 * The following are defines for the interrupt assignments.
58 #define INT_GPIOA 16 ///< GPIO Port A
59 #define INT_GPIOB 17 ///< GPIO Port B
60 #define INT_GPIOC 18 ///< GPIO Port C
61 #define INT_GPIOD 19 ///< GPIO Port D
62 #define INT_GPIOE 20 ///< GPIO Port E
63 #define INT_UART0 21 ///< UART0 Rx and Tx
64 #define INT_UART1 22 ///< UART1 Rx and Tx
65 #define INT_SSI0 23 ///< SSI0 Rx and Tx
66 #define INT_I2C0 24 ///< I2C0 Master and Slave
67 #define INT_PWM_FAULT 25 ///< PWM Fault
68 #define INT_PWM0 26 ///< PWM Generator 0
69 #define INT_PWM1 27 ///< PWM Generator 1
70 #define INT_PWM2 28 ///< PWM Generator 2
71 #define INT_QEI0 29 ///< Quadrature Encoder 0
72 #define INT_ADC0 30 ///< ADC Sequence 0
73 #define INT_ADC1 31 ///< ADC Sequence 1
74 #define INT_ADC2 32 ///< ADC Sequence 2
75 #define INT_ADC3 33 ///< ADC Sequence 3
76 #define INT_WATCHDOG 34 ///< Watchdog timer
77 #define INT_TIMER0A 35 ///< Timer 0 subtimer A
78 #define INT_TIMER0B 36 ///< Timer 0 subtimer B
79 #define INT_TIMER1A 37 ///< Timer 1 subtimer A
80 #define INT_TIMER1B 38 ///< Timer 1 subtimer B
81 #define INT_TIMER2A 39 ///< Timer 2 subtimer A
82 #define INT_TIMER2B 40 ///< Timer 2 subtimer B
83 #define INT_COMP0 41 ///< Analog Comparator 0
84 #define INT_COMP1 42 ///< Analog Comparator 1
85 #define INT_COMP2 43 ///< Analog Comparator 2
86 #define INT_SYSCTL 44 ///< System Control (PLL, OSC, BO)
87 #define INT_FLASH 45 ///< FLASH Control
88 #define INT_GPIOF 46 ///< GPIO Port F
89 #define INT_GPIOG 47 ///< GPIO Port G
90 #define INT_GPIOH 48 ///< GPIO Port H
91 #define INT_UART2 49 ///< UART2 Rx and Tx
92 #define INT_SSI1 50 ///< SSI1 Rx and Tx
93 #define INT_TIMER3A 51 ///< Timer 3 subtimer A
94 #define INT_TIMER3B 52 ///< Timer 3 subtimer B
95 #define INT_I2C1 53 ///< I2C1 Master and Slave
96 #define INT_QEI1 54 ///< Quadrature Encoder 1
97 #define INT_CAN0 55 ///< CAN0
98 #define INT_CAN1 56 ///< CAN1
99 #define INT_CAN2 57 ///< CAN2
100 #define INT_ETH 58 ///< Ethernet
101 #define INT_HIBERNATE 59 ///< Hibernation module
102 #define INT_USB0 60 ///< USB 0 Controller
103 #define INT_PWM3 61 ///< PWM Generator 3
104 #define INT_UDMA 62 ///< uDMA controller
105 #define INT_UDMAERR 63 ///< uDMA Error
106 #define INT_ADC1SS0 64 ///< ADC1 Sequence 0
107 #define INT_ADC1SS1 65 ///< ADC1 Sequence 1
108 #define INT_ADC1SS2 66 ///< ADC1 Sequence 2
109 #define INT_ADC1SS3 67 ///< ADC1 Sequence 3
110 #define INT_I2S0 68 ///< I2S0
111 #define INT_EPI0 69 ///< EPI0
112 #define INT_GPIOJ 70 ///< GPIO Port J
116 * The following are defines for the total number of interrupts.
119 #define NUM_INTERRUPTS 71
123 * The following are defines for the total number of priority levels.
126 #define NUM_PRIORITY 8
127 #define NUM_PRIORITY_BITS 3
130 #endif /* LM3S_INTS_H */