4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 memory map.
40 * The following are defines for the base address of the memories and
44 #define FLASH_BASE 0x00000000 //< FLASH memory
45 #define SRAM_BASE 0x20000000 //< SRAM memory
46 #define WATCHDOG0_BASE 0x40000000 //< Watchdog0
47 #define WATCHDOG1_BASE 0x40001000 //< Watchdog1
48 #define GPIO_PORTA_BASE 0x40004000 //< GPIO Port A
49 #define GPIO_PORTB_BASE 0x40005000 //< GPIO Port B
50 #define GPIO_PORTC_BASE 0x40006000 //< GPIO Port C
51 #define GPIO_PORTD_BASE 0x40007000 //< GPIO Port D
52 #define SSI0_BASE 0x40008000 //< SSI0
53 #define SSI1_BASE 0x40009000 //< SSI1
54 #define UART0_BASE 0x4000C000 //< UART0
55 #define UART1_BASE 0x4000D000 //< UART1
56 #define UART2_BASE 0x4000E000 //< UART2
57 #define I2C0_MASTER_BASE 0x40020000 //< I2C0 Master
58 #define I2C0_SLAVE_BASE 0x40020800 //< I2C0 Slave
59 #define I2C1_MASTER_BASE 0x40021000 //< I2C1 Master
60 #define I2C1_SLAVE_BASE 0x40021800 //< I2C1 Slave
61 #define GPIO_PORTE_BASE 0x40024000 //< GPIO Port E
62 #define GPIO_PORTF_BASE 0x40025000 //< GPIO Port F
63 #define GPIO_PORTG_BASE 0x40026000 //< GPIO Port G
64 #define GPIO_PORTH_BASE 0x40027000 //< GPIO Port H
65 #define PWM_BASE 0x40028000 //< PWM
66 #define QEI0_BASE 0x4002C000 //< QEI0
67 #define QEI1_BASE 0x4002D000 //< QEI1
68 #define TIMER0_BASE 0x40030000 //< Timer0
69 #define TIMER1_BASE 0x40031000 //< Timer1
70 #define TIMER2_BASE 0x40032000 //< Timer2
71 #define TIMER3_BASE 0x40033000 //< Timer3
72 #define ADC0_BASE 0x40038000 //< ADC0
73 #define ADC1_BASE 0x40039000 //< ADC1
74 #define COMP_BASE 0x4003C000 //< Analog comparators
75 #define GPIO_PORTJ_BASE 0x4003D000 //< GPIO Port J
76 #define CAN0_BASE 0x40040000 //< CAN0
77 #define CAN1_BASE 0x40041000 //< CAN1
78 #define CAN2_BASE 0x40042000 //< CAN2
79 #define ETH_BASE 0x40048000 //< Ethernet
80 #define MAC_BASE 0x40048000 //< Ethernet
81 #define USB0_BASE 0x40050000 //< USB 0 Controller
82 #define I2S0_BASE 0x40054000 //< I2S0
83 #define GPIO_PORTA_AHB_BASE 0x40058000 //< GPIO Port A (high speed)
84 #define GPIO_PORTB_AHB_BASE 0x40059000 //< GPIO Port B (high speed)
85 #define GPIO_PORTC_AHB_BASE 0x4005A000 //< GPIO Port C (high speed)
86 #define GPIO_PORTD_AHB_BASE 0x4005B000 //< GPIO Port D (high speed)
87 #define GPIO_PORTE_AHB_BASE 0x4005C000 //< GPIO Port E (high speed)
88 #define GPIO_PORTF_AHB_BASE 0x4005D000 //< GPIO Port F (high speed)
89 #define GPIO_PORTG_AHB_BASE 0x4005E000 //< GPIO Port G (high speed)
90 #define GPIO_PORTH_AHB_BASE 0x4005F000 //< GPIO Port H (high speed)
91 #define GPIO_PORTJ_AHB_BASE 0x40060000 //< GPIO Port J (high speed)
92 #define EPI0_BASE 0x400D0000 //< EPI0
93 #define HIB_BASE 0x400FC000 //< Hibernation Module
94 #define FLASH_CTRL_BASE 0x400FD000 //< FLASH Controller
95 #define SYSCTL_BASE 0x400FE000 //< System Control
96 #define UDMA_BASE 0x400FF000 //< uDMA Controller
97 #define ITM_BASE 0xE0000000 //< Instrumentation Trace Macrocell
98 #define DWT_BASE 0xE0001000 //< Data Watchpoint and Trace
99 #define FPB_BASE 0xE0002000 //< FLASH Patch and Breakpoint
100 #define NVIC_BASE 0xE000E000 //< Nested Vectored Interrupt Ctrl
101 #define TPIU_BASE 0xE0040000 //< Trace Port Interface Unit
105 * The following definitions are deprecated.
111 #define WATCHDOG_BASE 0x40000000 //< Watchdog
112 #define SSI_BASE 0x40008000 //< SSI
113 #define I2C_MASTER_BASE 0x40020000 //< I2C Master
114 #define I2C_SLAVE_BASE 0x40020800 //< I2C Slave
115 #define QEI_BASE 0x4002C000 //< QEI
116 #define ADC_BASE 0x40038000 //< ADC
118 #endif /* DEPRECATED */
120 #endif /* LM3S_MEMMAP_H */