4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 SSI hardware definitions.
40 * The following are defines for the SSI register offsets.
43 #define SSI_O_CR0 0x00000000 //< SSI Control 0
44 #define SSI_O_CR1 0x00000004 //< SSI Control 1
45 #define SSI_O_DR 0x00000008 //< SSI Data
46 #define SSI_O_SR 0x0000000C //< SSI Status
47 #define SSI_O_CPSR 0x00000010 //< SSI Clock Prescale
48 #define SSI_O_IM 0x00000014 //< SSI Interrupt Mask
49 #define SSI_O_RIS 0x00000018 //< SSI Raw Interrupt Status
50 #define SSI_O_MIS 0x0000001C //< SSI Masked Interrupt Status
51 #define SSI_O_ICR 0x00000020 //< SSI Interrupt Clear
52 #define SSI_O_DMACTL 0x00000024 //< SSI DMA Control
56 * The following are defines for the bit fields in the SSI_O_CR0 register.
59 #define SSI_CR0_SCR_M 0x0000FF00 //< SSI Serial Clock Rate
60 #define SSI_CR0_SPH 0x00000080 //< SSI Serial Clock Phase
61 #define SSI_CR0_SPO 0x00000040 //< SSI Serial Clock Polarity
62 #define SSI_CR0_FRF_M 0x00000030 //< SSI Frame Format Select
63 #define SSI_CR0_FRF_MOTO 0x00000000 //< Freescale SPI Frame Format
64 #define SSI_CR0_FRF_TI 0x00000010 //< Texas Instruments Synchronous
65 //< Serial Frame Format
66 #define SSI_CR0_FRF_NMW 0x00000020 //< MICROWIRE Frame Format
67 #define SSI_CR0_DSS_M 0x0000000F //< SSI Data Size Select
68 #define SSI_CR0_DSS_4 0x00000003 //< 4-bit data
69 #define SSI_CR0_DSS_5 0x00000004 //< 5-bit data
70 #define SSI_CR0_DSS_6 0x00000005 //< 6-bit data
71 #define SSI_CR0_DSS_7 0x00000006 //< 7-bit data
72 #define SSI_CR0_DSS_8 0x00000007 //< 8-bit data
73 #define SSI_CR0_DSS_9 0x00000008 //< 9-bit data
74 #define SSI_CR0_DSS_10 0x00000009 //< 10-bit data
75 #define SSI_CR0_DSS_11 0x0000000A //< 11-bit data
76 #define SSI_CR0_DSS_12 0x0000000B //< 12-bit data
77 #define SSI_CR0_DSS_13 0x0000000C //< 13-bit data
78 #define SSI_CR0_DSS_14 0x0000000D //< 14-bit data
79 #define SSI_CR0_DSS_15 0x0000000E //< 15-bit data
80 #define SSI_CR0_DSS_16 0x0000000F //< 16-bit data
81 #define SSI_CR0_SCR_S 8
85 * The following are defines for the bit fields in the SSI_O_CR1 register.
88 #define SSI_CR1_EOT 0x00000010 //< End of Transmission
89 #define SSI_CR1_SOD 0x00000008 //< SSI Slave Mode Output Disable
90 #define SSI_CR1_MS 0x00000004 //< SSI Master/Slave Select
91 #define SSI_CR1_SSE 0x00000002 //< SSI Synchronous Serial Port
93 #define SSI_CR1_LBM 0x00000001 //< SSI Loopback Mode
97 * The following are defines for the bit fields in the SSI_O_DR register.
100 #define SSI_DR_DATA_M 0x0000FFFF //< SSI Receive/Transmit Data
101 #define SSI_DR_DATA_S 0
105 * The following are defines for the bit fields in the SSI_O_SR register.
108 #define SSI_SR_BSY 0x00000010 //< SSI Busy Bit
109 #define SSI_SR_RFF 0x00000008 //< SSI Receive FIFO Full
110 #define SSI_SR_RNE 0x00000004 //< SSI Receive FIFO Not Empty
111 #define SSI_SR_TNF 0x00000002 //< SSI Transmit FIFO Not Full
112 #define SSI_SR_TFE 0x00000001 //< SSI Transmit FIFO Empty
116 * The following are defines for the bit fields in the SSI_O_CPSR register.
119 #define SSI_CPSR_CPSDVSR_M 0x000000FF //< SSI Clock Prescale Divisor
120 #define SSI_CPSR_CPSDVSR_S 0
124 * The following are defines for the bit fields in the SSI_O_IM register.
127 #define SSI_IM_TXIM 0x00000008 //< SSI Transmit FIFO Interrupt Mask
128 #define SSI_IM_RXIM 0x00000004 //< SSI Receive FIFO Interrupt Mask
129 #define SSI_IM_RTIM 0x00000002 //< SSI Receive Time-Out Interrupt
131 #define SSI_IM_RORIM 0x00000001 //< SSI Receive Overrun Interrupt
136 * The following are defines for the bit fields in the SSI_O_RIS register.
139 #define SSI_RIS_TXRIS 0x00000008 //< SSI Transmit FIFO Raw Interrupt
141 #define SSI_RIS_RXRIS 0x00000004 //< SSI Receive FIFO Raw Interrupt
143 #define SSI_RIS_RTRIS 0x00000002 //< SSI Receive Time-Out Raw
145 #define SSI_RIS_RORRIS 0x00000001 //< SSI Receive Overrun Raw
150 * The following are defines for the bit fields in the SSI_O_MIS register.
153 #define SSI_MIS_TXMIS 0x00000008 //< SSI Transmit FIFO Masked
155 #define SSI_MIS_RXMIS 0x00000004 //< SSI Receive FIFO Masked
157 #define SSI_MIS_RTMIS 0x00000002 //< SSI Receive Time-Out Masked
159 #define SSI_MIS_RORMIS 0x00000001 //< SSI Receive Overrun Masked
164 * The following are defines for the bit fields in the SSI_O_ICR register.
167 #define SSI_ICR_RTIC 0x00000002 //< SSI Receive Time-Out Interrupt
169 #define SSI_ICR_RORIC 0x00000001 //< SSI Receive Overrun Interrupt
174 * The following are defines for the bit fields in the SSI_O_DMACTL register.
177 #define SSI_DMACTL_TXDMAE 0x00000002 //< Transmit DMA Enable
178 #define SSI_DMACTL_RXDMAE 0x00000001 //< Receive DMA Enable
182 * The following definitions are deprecated.
189 * The following are deprecated defines for the bit fields in the SSI_O_CR0
193 #define SSI_CR0_SCR 0x0000FF00 //< Serial clock rate
194 #define SSI_CR0_FRF_MASK 0x00000030 //< Frame format mask
195 #define SSI_CR0_DSS 0x0000000F //< Data size select
199 * The following are deprecated defines for the bit fields in the SSI_O_CPSR
203 #define SSI_CPSR_CPSDVSR_MASK 0x000000FF //< Clock prescale
207 * The following are deprecated defines for the SSI controller's FIFO size.
210 #define TX_FIFO_SIZE (8) //< Number of entries in the TX FIFO
211 #define RX_FIFO_SIZE (8) //< Number of entries in the RX FIFO
215 * The following are deprecated defines for the bit fields in the interrupt
216 * mask set and clear, raw interrupt, masked interrupt, and interrupt clear
220 #define SSI_INT_TXFF 0x00000008 //< TX FIFO interrupt
221 #define SSI_INT_RXFF 0x00000004 //< RX FIFO interrupt
222 #define SSI_INT_RXTO 0x00000002 //< RX timeout interrupt
223 #define SSI_INT_RXOR 0x00000001 //< RX overrun interrupt
226 #endif /* DEPRECATED */
228 #endif /* LM3S_SSI_H */