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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 UART hardware.
40 * The following are defines for the UART register offsets.
43 #define UART_O_DR 0x00000000 //< UART Data
44 #define UART_O_RSR 0x00000004 //< UART Receive Status/Error Clear
45 #define UART_O_ECR 0x00000004 //< UART Receive Status/Error Clear
46 #define UART_O_FR 0x00000018 //< UART Flag
47 #define UART_O_ILPR 0x00000020 //< UART IrDA Low-Power Register
48 #define UART_O_IBRD 0x00000024 //< UART Integer Baud-Rate Divisor
49 #define UART_O_FBRD 0x00000028 //< UART Fractional Baud-Rate
51 #define UART_O_LCRH 0x0000002C //< UART Line Control
52 #define UART_O_CTL 0x00000030 //< UART Control
53 #define UART_O_IFLS 0x00000034 //< UART Interrupt FIFO Level Select
54 #define UART_O_IM 0x00000038 //< UART Interrupt Mask
55 #define UART_O_RIS 0x0000003C //< UART Raw Interrupt Status
56 #define UART_O_MIS 0x00000040 //< UART Masked Interrupt Status
57 #define UART_O_ICR 0x00000044 //< UART Interrupt Clear
58 #define UART_O_DMACTL 0x00000048 //< UART DMA Control
59 #define UART_O_LCTL 0x00000090 //< UART LIN Control
60 #define UART_O_LSS 0x00000094 //< UART LIN Snap Shot
61 #define UART_O_LTIM 0x00000098 //< UART LIN Timer
65 * The following are defines for the bit fields in the UART_O_DR register.
68 #define UART_DR_OE 0x00000800 //< UART Overrun Error
69 #define UART_DR_BE 0x00000400 //< UART Break Error
70 #define UART_DR_PE 0x00000200 //< UART Parity Error
71 #define UART_DR_FE 0x00000100 //< UART Framing Error
72 #define UART_DR_DATA_M 0x000000FF //< Data Transmitted or Received
73 #define UART_DR_DATA_S 0
77 * The following are defines for the bit fields in the UART_O_RSR register.
80 #define UART_RSR_OE 0x00000008 //< UART Overrun Error
81 #define UART_RSR_BE 0x00000004 //< UART Break Error
82 #define UART_RSR_PE 0x00000002 //< UART Parity Error
83 #define UART_RSR_FE 0x00000001 //< UART Framing Error
87 * The following are defines for the bit fields in the UART_O_ECR register.
90 #define UART_ECR_DATA_M 0x000000FF //< Error Clear
91 #define UART_ECR_DATA_S 0
95 * The following are defines for the bit fields in the UART_O_FR register.
98 #define UART_FR_RI 0x00000100 //< Ring Indicator
99 #define UART_FR_TXFE 0x00000080 //< UART Transmit FIFO Empty
100 #define UART_FR_RXFF 0x00000040 //< UART Receive FIFO Full
101 #define UART_FR_TXFF 0x00000020 //< UART Transmit FIFO Full
102 #define UART_FR_RXFE 0x00000010 //< UART Receive FIFO Empty
103 #define UART_FR_BUSY 0x00000008 //< UART Busy
104 #define UART_FR_DCD 0x00000004 //< Data Carrier Detect
105 #define UART_FR_DSR 0x00000002 //< Data Set Ready
106 #define UART_FR_CTS 0x00000001 //< Clear To Send
110 * The following are defines for the bit fields in the UART_O_ILPR register.
113 #define UART_ILPR_ILPDVSR_M 0x000000FF //< IrDA Low-Power Divisor
114 #define UART_ILPR_ILPDVSR_S 0
118 * The following are defines for the bit fields in the UART_O_IBRD register.
121 #define UART_IBRD_DIVINT_M 0x0000FFFF //< Integer Baud-Rate Divisor
122 #define UART_IBRD_DIVINT_S 0
126 * The following are defines for the bit fields in the UART_O_FBRD register.
129 #define UART_FBRD_DIVFRAC_M 0x0000003F //< Fractional Baud-Rate Divisor
130 #define UART_FBRD_DIVFRAC_S 0
134 * The following are defines for the bit fields in the UART_O_LCRH register.
137 #define UART_LCRH_SPS 0x00000080 //< UART Stick Parity Select
138 #define UART_LCRH_WLEN_M 0x00000060 //< UART Word Length
139 #define UART_LCRH_WLEN_5 0x00000000 //< 5 bits (default)
140 #define UART_LCRH_WLEN_6 0x00000020 //< 6 bits
141 #define UART_LCRH_WLEN_7 0x00000040 //< 7 bits
142 #define UART_LCRH_WLEN_8 0x00000060 //< 8 bits
143 #define UART_LCRH_FEN 0x00000010 //< UART Enable FIFOs
144 #define UART_LCRH_STP2 0x00000008 //< UART Two Stop Bits Select
145 #define UART_LCRH_EPS 0x00000004 //< UART Even Parity Select
146 #define UART_LCRH_PEN 0x00000002 //< UART Parity Enable
147 #define UART_LCRH_BRK 0x00000001 //< UART Send Break
151 * The following are defines for the bit fields in the UART_O_CTL register.
154 #define UART_CTL_CTSEN 0x00008000 //< Enable Clear To Send
155 #define UART_CTL_RTSEN 0x00004000 //< Enable Request to Send
156 #define UART_CTL_RTS 0x00000800 //< Request to Send
157 #define UART_CTL_DTR 0x00000400 //< Data Terminal Ready
158 #define UART_CTL_RXE 0x00000200 //< UART Receive Enable
159 #define UART_CTL_TXE 0x00000100 //< UART Transmit Enable
160 #define UART_CTL_LBE 0x00000080 //< UART Loop Back Enable
161 #define UART_CTL_LIN 0x00000040 //< LIN Mode Enable
162 #define UART_CTL_HSE 0x00000020 //< High-Speed Enable
163 #define UART_CTL_EOT 0x00000010 //< End of Transmission
164 #define UART_CTL_SMART 0x00000008 //< ISO 7816 Smart Card Support
165 #define UART_CTL_SIRLP 0x00000004 //< UART SIR Low-Power Mode
166 #define UART_CTL_SIREN 0x00000002 //< UART SIR Enable
167 #define UART_CTL_UARTEN 0x00000001 //< UART Enable
171 * The following are defines for the bit fields in the UART_O_IFLS register.
174 #define UART_IFLS_RX_M 0x00000038 //< UART Receive Interrupt FIFO
176 #define UART_IFLS_RX1_8 0x00000000 //< RX FIFO >= 1/8 full
177 #define UART_IFLS_RX2_8 0x00000008 //< RX FIFO >= 1/4 full
178 #define UART_IFLS_RX4_8 0x00000010 //< RX FIFO >= 1/2 full (default)
179 #define UART_IFLS_RX6_8 0x00000018 //< RX FIFO >= 3/4 full
180 #define UART_IFLS_RX7_8 0x00000020 //< RX FIFO >= 7/8 full
181 #define UART_IFLS_TX_M 0x00000007 //< UART Transmit Interrupt FIFO
183 #define UART_IFLS_TX1_8 0x00000000 //< TX FIFO <= 1/8 full
184 #define UART_IFLS_TX2_8 0x00000001 //< TX FIFO <= 1/4 full
185 #define UART_IFLS_TX4_8 0x00000002 //< TX FIFO <= 1/2 full (default)
186 #define UART_IFLS_TX6_8 0x00000003 //< TX FIFO <= 3/4 full
187 #define UART_IFLS_TX7_8 0x00000004 //< TX FIFO <= 7/8 full
191 * The following are defines for the bit fields in the UART_O_IM register.
194 #define UART_IM_LME5IM 0x00008000 //< LIN Mode Edge 5 Interrupt Mask
195 #define UART_IM_LME1IM 0x00004000 //< LIN Mode Edge 1 Interrupt Mask
196 #define UART_IM_LMSBIM 0x00002000 //< LIN Mode Sync Break Interrupt
198 #define UART_IM_OEIM 0x00000400 //< UART Overrun Error Interrupt
200 #define UART_IM_BEIM 0x00000200 //< UART Break Error Interrupt Mask
201 #define UART_IM_PEIM 0x00000100 //< UART Parity Error Interrupt Mask
202 #define UART_IM_FEIM 0x00000080 //< UART Framing Error Interrupt
204 #define UART_IM_RTIM 0x00000040 //< UART Receive Time-Out Interrupt
206 #define UART_IM_TXIM 0x00000020 //< UART Transmit Interrupt Mask
207 #define UART_IM_RXIM 0x00000010 //< UART Receive Interrupt Mask
208 #define UART_IM_DSRMIM 0x00000008 //< UART Data Set Ready Modem
210 #define UART_IM_DCDMIM 0x00000004 //< UART Data Carrier Detect Modem
212 #define UART_IM_CTSMIM 0x00000002 //< UART Clear to Send Modem
214 #define UART_IM_RIMIM 0x00000001 //< UART Ring Indicator Modem
219 * The following are defines for the bit fields in the UART_O_RIS register.
222 #define UART_RIS_LME5RIS 0x00008000 //< LIN Mode Edge 5 Raw Interrupt
224 #define UART_RIS_LME1RIS 0x00004000 //< LIN Mode Edge 1 Raw Interrupt
226 #define UART_RIS_LMSBRIS 0x00002000 //< LIN Mode Sync Break Raw
228 #define UART_RIS_OERIS 0x00000400 //< UART Overrun Error Raw Interrupt
230 #define UART_RIS_BERIS 0x00000200 //< UART Break Error Raw Interrupt
232 #define UART_RIS_PERIS 0x00000100 //< UART Parity Error Raw Interrupt
234 #define UART_RIS_FERIS 0x00000080 //< UART Framing Error Raw Interrupt
236 #define UART_RIS_RTRIS 0x00000040 //< UART Receive Time-Out Raw
238 #define UART_RIS_TXRIS 0x00000020 //< UART Transmit Raw Interrupt
240 #define UART_RIS_RXRIS 0x00000010 //< UART Receive Raw Interrupt
242 #define UART_RIS_DSRRIS 0x00000008 //< UART Data Set Ready Modem Raw
244 #define UART_RIS_DCDRIS 0x00000004 //< UART Data Carrier Detect Modem
245 //< Raw Interrupt Status
246 #define UART_RIS_CTSRIS 0x00000002 //< UART Clear to Send Modem Raw
248 #define UART_RIS_RIRIS 0x00000001 //< UART Ring Indicator Modem Raw
253 * The following are defines for the bit fields in the UART_O_MIS register.
256 #define UART_MIS_LME5MIS 0x00008000 //< LIN Mode Edge 5 Masked Interrupt
258 #define UART_MIS_LME1MIS 0x00004000 //< LIN Mode Edge 1 Masked Interrupt
260 #define UART_MIS_LMSBMIS 0x00002000 //< LIN Mode Sync Break Masked
262 #define UART_MIS_OEMIS 0x00000400 //< UART Overrun Error Masked
264 #define UART_MIS_BEMIS 0x00000200 //< UART Break Error Masked
266 #define UART_MIS_PEMIS 0x00000100 //< UART Parity Error Masked
268 #define UART_MIS_FEMIS 0x00000080 //< UART Framing Error Masked
270 #define UART_MIS_RTMIS 0x00000040 //< UART Receive Time-Out Masked
272 #define UART_MIS_TXMIS 0x00000020 //< UART Transmit Masked Interrupt
274 #define UART_MIS_RXMIS 0x00000010 //< UART Receive Masked Interrupt
276 #define UART_MIS_DSRMIS 0x00000008 //< UART Data Set Ready Modem Masked
278 #define UART_MIS_DCDMIS 0x00000004 //< UART Data Carrier Detect Modem
279 //< Masked Interrupt Status
280 #define UART_MIS_CTSMIS 0x00000002 //< UART Clear to Send Modem Masked
282 #define UART_MIS_RIMIS 0x00000001 //< UART Ring Indicator Modem Masked
287 * The following are defines for the bit fields in the UART_O_ICR register.
290 #define UART_ICR_LME5MIC 0x00008000 //< LIN Mode Edge 5 Interrupt Clear
291 #define UART_ICR_LME1MIC 0x00004000 //< LIN Mode Edge 1 Interrupt Clear
292 #define UART_ICR_LMSBMIC 0x00002000 //< LIN Mode Sync Break Interrupt
294 #define UART_ICR_OEIC 0x00000400 //< Overrun Error Interrupt Clear
295 #define UART_ICR_BEIC 0x00000200 //< Break Error Interrupt Clear
296 #define UART_ICR_PEIC 0x00000100 //< Parity Error Interrupt Clear
297 #define UART_ICR_FEIC 0x00000080 //< Framing Error Interrupt Clear
298 #define UART_ICR_RTIC 0x00000040 //< Receive Time-Out Interrupt Clear
299 #define UART_ICR_TXIC 0x00000020 //< Transmit Interrupt Clear
300 #define UART_ICR_RXIC 0x00000010 //< Receive Interrupt Clear
301 #define UART_ICR_DSRMIC 0x00000008 //< UART Data Set Ready Modem
303 #define UART_ICR_DCDMIC 0x00000004 //< UART Data Carrier Detect Modem
305 #define UART_ICR_CTSMIC 0x00000002 //< UART Clear to Send Modem
307 #define UART_ICR_RIMIC 0x00000001 //< UART Ring Indicator Modem
312 * The following are defines for the bit fields in the UART_O_DMACTL register.
315 #define UART_DMACTL_DMAERR 0x00000004 //< DMA on Error
316 #define UART_DMACTL_TXDMAE 0x00000002 //< Transmit DMA Enable
317 #define UART_DMACTL_RXDMAE 0x00000001 //< Receive DMA Enable
321 * The following are defines for the bit fields in the UART_O_LCTL register.
324 #define UART_LCTL_BLEN_M 0x00000030 //< Sync Break Length
325 #define UART_LCTL_BLEN_13T 0x00000000 //< Sync break length is 13T bits
327 #define UART_LCTL_BLEN_14T 0x00000010 //< Sync break length is 14T bits
328 #define UART_LCTL_BLEN_15T 0x00000020 //< Sync break length is 15T bits
329 #define UART_LCTL_BLEN_16T 0x00000030 //< Sync break length is 16T bits
330 #define UART_LCTL_MASTER 0x00000001 //< LIN Master Enable
334 * The following are defines for the bit fields in the UART_O_LSS register.
337 #define UART_LSS_TSS_M 0x0000FFFF //< Timer Snap Shot
338 #define UART_LSS_TSS_S 0
342 * The following are defines for the bit fields in the UART_O_LTIM register.
345 #define UART_LTIM_TIMER_M 0x0000FFFF //< Timer Value
346 #define UART_LTIM_TIMER_S 0
350 * The following definitions are deprecated.
357 * The following are deprecated defines for the UART register offsets.
360 #define UART_O_LCR_H 0x0000002C //< Line Control Register, HIGH byte
361 #define UART_O_PeriphID4 0x00000FD0
362 #define UART_O_PeriphID5 0x00000FD4
363 #define UART_O_PeriphID6 0x00000FD8
364 #define UART_O_PeriphID7 0x00000FDC
365 #define UART_O_PeriphID0 0x00000FE0
366 #define UART_O_PeriphID1 0x00000FE4
367 #define UART_O_PeriphID2 0x00000FE8
368 #define UART_O_PeriphID3 0x00000FEC
369 #define UART_O_PCellID0 0x00000FF0
370 #define UART_O_PCellID1 0x00000FF4
371 #define UART_O_PCellID2 0x00000FF8
372 #define UART_O_PCellID3 0x00000FFC
376 * The following are deprecated defines for the bit fields in the UART_O_DR
380 #define UART_DR_DATA_MASK 0x000000FF //< UART data
384 * The following are deprecated defines for the bit fields in the UART_O_IBRD
388 #define UART_IBRD_DIVINT_MASK 0x0000FFFF //< Integer baud-rate divisor
392 * The following are deprecated defines for the bit fields in the UART_O_FBRD
396 #define UART_FBRD_DIVFRAC_MASK 0x0000003F //< Fractional baud-rate divisor
400 * The following are deprecated defines for the bit fields in the UART_O_LCR_H
404 #define UART_LCR_H_SPS 0x00000080 //< Stick Parity Select
405 #define UART_LCR_H_WLEN 0x00000060 //< Word length
406 #define UART_LCR_H_WLEN_5 0x00000000 //< 5 bit data
407 #define UART_LCR_H_WLEN_6 0x00000020 //< 6 bit data
408 #define UART_LCR_H_WLEN_7 0x00000040 //< 7 bit data
409 #define UART_LCR_H_WLEN_8 0x00000060 //< 8 bit data
410 #define UART_LCR_H_FEN 0x00000010 //< Enable FIFO
411 #define UART_LCR_H_STP2 0x00000008 //< Two Stop Bits Select
412 #define UART_LCR_H_EPS 0x00000004 //< Even Parity Select
413 #define UART_LCR_H_PEN 0x00000002 //< Parity Enable
414 #define UART_LCR_H_BRK 0x00000001 //< Send Break
418 * The following are deprecated defines for the bit fields in the UART_O_IFLS
422 #define UART_IFLS_RX_MASK 0x00000038 //< RX FIFO level mask
423 #define UART_IFLS_TX_MASK 0x00000007 //< TX FIFO level mask
427 * The following are deprecated defines for the bit fields in the UART_O_ICR
431 #define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
436 * The following are deprecated defines for the Reset Values for UART
440 #define UART_RV_CTL 0x00000300
441 #define UART_RV_PCellID1 0x000000F0
442 #define UART_RV_PCellID3 0x000000B1
443 #define UART_RV_FR 0x00000090
444 #define UART_RV_PeriphID2 0x00000018
445 #define UART_RV_IFLS 0x00000012
446 #define UART_RV_PeriphID0 0x00000011
447 #define UART_RV_PCellID0 0x0000000D
448 #define UART_RV_PCellID2 0x00000005
449 #define UART_RV_PeriphID3 0x00000001
450 #define UART_RV_PeriphID4 0x00000000
451 #define UART_RV_LCR_H 0x00000000
452 #define UART_RV_PeriphID6 0x00000000
453 #define UART_RV_DR 0x00000000
454 #define UART_RV_RSR 0x00000000
455 #define UART_RV_ECR 0x00000000
456 #define UART_RV_PeriphID5 0x00000000
457 #define UART_RV_RIS 0x00000000
458 #define UART_RV_FBRD 0x00000000
459 #define UART_RV_IM 0x00000000
460 #define UART_RV_MIS 0x00000000
461 #define UART_RV_ICR 0x00000000
462 #define UART_RV_PeriphID1 0x00000000
463 #define UART_RV_PeriphID7 0x00000000
464 #define UART_RV_IBRD 0x00000000
467 #endif /* DEPRECATED */
469 #endif /* LM3S_UART_H */