4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
33 * \author Stefano Fedrigo <aleph@develer.com>
39 #include <cpu/detect.h>
40 #include <cfg/compiler.h>
47 #define SUPC_ID 0 ///< Supply Controller (SUPC)
48 #define RSTC_ID 1 ///< Reset Controller (RSTC)
49 #define RTC_ID 2 ///< Real Time Clock (RTC)
50 #define RTT_ID 3 ///< Real Time Timer (RTT)
51 #define WDT_ID 4 ///< Watchdog Timer (WDT)
52 #define PMC_ID 5 ///< Power Management Controller (PMC)
53 #define EEFC0_ID 6 ///< Enhanced Flash Controller
54 #define UART0_ID 8 ///< UART 0 (UART0)
55 #define UART1_ID 9 ///< UART 1 (UART1)
56 #define PIOA_ID 11 ///< Parallel I/O Controller A (PIOA)
57 #define PIOB_ID 12 ///< Parallel I/O Controller B (PIOB)
58 #define PIOC_ID 13 ///< Parallel I/O Controller C (PIOC)
59 #define US0_ID 14 ///< USART 0 (USART0)
60 #define US1_ID 15 ///< USART 1 (USART1)
61 #define TWI0_ID 19 ///< Two Wire Interface 0 (TWI0)
62 #define TWI1_ID 20 ///< Two Wire Interface 1 (TWI1)
63 #define SPI0_ID 21 ///< Serial Peripheral Interface (SPI)
64 #define TC0_ID 23 ///< Timer/Counter 0 (TC0)
65 #define TC1_ID 24 ///< Timer/Counter 1 (TC1)
66 #define TC2_ID 25 ///< Timer/Counter 2 (TC2)
67 #define TC3_ID 26 ///< Timer/Counter 3 (TC3)
68 #define TC4_ID 27 ///< Timer/Counter 4 (TC4)
69 #define TC5_ID 28 ///< Timer/Counter 5 (TC5)
70 #define ADC_ID 29 ///< Analog To Digital Converter (ADC)
71 #define DACC_ID 30 ///< Digital To Analog Converter (DACC)
72 #define PWM_ID 31 ///< Pulse Width Modulation (PWM)
74 #define SUPC_ID 0 ///< Supply Controller (SUPC)
75 #define RSTC_ID 1 ///< Reset Controller (RSTC)
76 #define RTC_ID 2 ///< Real Time Clock (RTC)
77 #define RTT_ID 3 ///< Real Time Timer (RTT)
78 #define WDT_ID 4 ///< Watchdog Timer (WDT)
79 #define PMC_ID 5 ///< Power Management Controller (PMC)
80 #define EEFC0_ID 6 ///< Enhanced Flash Controller
81 #define EEFC1_ID 7 ///< Enhanced Flash Controller
82 #define UART0_ID 8 ///< UART 0 (UART0)
83 #define SMC_SDRAMC_ID 9 ///< Satic memory controller / SDRAM controller
84 #define SDRAMC_ID 10 ///< Satic memory controller / SDRAM controller
85 #define PIOA_ID 11 ///< Parallel I/O Controller A
86 #define PIOB_ID 12 ///< Parallel I/O Controller B
87 #define PIOC_ID 13 ///< Parallel I/O Controller C
88 #define PIOD_ID 14 ///< Parallel I/O Controller D
89 #define PIOE_ID 15 ///< Parallel I/O Controller E
90 #define PIOF_ID 16 ///< Parallel I/O Controller F
91 #define US0_ID 17 ///< USART 0
92 #define US1_ID 18 ///< USART 1
93 #define US2_ID 19 ///< USART 2
94 #define US3_ID 20 ///< USART 3
95 #define HSMCI_ID 21 ///< High speed multimedia card interface
96 #define TWI0_ID 22 ///< Two Wire Interface 0
97 #define TWI1_ID 23 ///< Two Wire Interface 1
98 #define SPI0_ID 24 ///< Serial Peripheral Interface
99 #define SPI1_ID 25 ///< Serial Peripheral Interface
100 #define SSC_ID 26 ///< Synchronous serial controller
101 #define TC0_ID 27 ///< Timer/Counter 0
102 #define TC1_ID 28 ///< Timer/Counter 1
103 #define TC2_ID 29 ///< Timer/Counter 2
104 #define TC3_ID 30 ///< Timer/Counter 3
105 #define TC4_ID 31 ///< Timer/Counter 4
106 #define TC5_ID 32 ///< Timer/Counter 5
107 #define TC6_ID 33 ///< Timer/Counter 6
108 #define TC7_ID 34 ///< Timer/Counter 7
109 #define TC8_ID 35 ///< Timer/Counter 8
110 #define PWM_ID 36 ///< Pulse width modulation controller
111 #define ADC_ID 37 ///< ADC controller
112 #define DACC_ID 38 ///< DAC controller
113 #define DMAC_ID 39 ///< DMA controller
114 #define UOTGHS_ID 40 ///< USB OTG high speed
115 #define TRNG_ID 41 ///< True random number generator
116 #define EMAC_ID 42 ///< Ethernet MAC
117 #define CAN0_ID 43 ///< CAN controller 0
118 #define CAN1_ID 44 ///< CAN controller 1
120 #error Peripheral IDs undefined
125 * Hardware features for drivers.
127 #define USART_HAS_PDC 1
128 #define SPI_HAS_PDC 1
130 #if CPU_CM3_SAM3X || CPU_CM3_SAM3U
131 #define USART_PORTS 1
133 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
134 #define USART_PORTS 2
137 #error undefined U(S)ART_PORTS for this cpu
140 #include "sam3_sysctl.h"
141 #include "sam3_pdc.h"
142 #include "sam3_pmc.h"
143 #include "sam3_dmac.h"
144 #include "sam3_smc.h"
145 #include "sam3_sdramc.h"
146 #include "sam3_ints.h"
147 #include "sam3_pio.h"
148 #include "sam3_nvic.h"
149 #include "sam3_uart.h"
150 #include "sam3_usart.h"
151 #include "sam3_spi.h"
152 #include "sam3_flash.h"
153 #include "sam3_wdt.h"
154 #include "sam3_emac.h"
155 #include "sam3_rstc.h"
156 #include "sam3_adc.h"
157 #include "sam3_dacc.h"
159 #include "sam3_twi.h"
160 #include "sam3_ssc.h"
161 #include "sam3_hsmci.h"
168 #define UART0_PORT PIOA_BASE
169 #define USART0_PORT PIOA_BASE
170 #define USART1_PORT PIOA_BASE
171 #define USART2_PORT PIOA_BASE
172 #define USART3_PORT PIOC_BASE
174 #define UART0_PERIPH PIO_PERIPH_A
175 #define USART0_PERIPH PIO_PERIPH_A
176 #define USART1_PERIPH PIO_PERIPH_A
177 #define USART2_PERIPH PIO_PERIPH_A
178 #define USART3_PERIPH PIO_PERIPH_B
191 #define UART0_PORT PIOA_BASE
192 #define USART0_PORT PIOA_BASE
193 #define USART1_PORT PIOA_BASE
194 #define USART2_PORT PIOB_BASE
195 #define USART3_PORT PIOD_BASE
197 #define UART0_PERIPH PIO_PERIPH_A
198 #define USART0_PERIPH PIO_PERIPH_A
199 #define USART1_PERIPH PIO_PERIPH_A
200 #define USART2_PERIPH PIO_PERIPH_A
201 #define USART3_PERIPH PIO_PERIPH_B
213 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
214 #define UART0_PORT PIOA_BASE
215 #define UART1_PORT PIOB_BASE
216 #define USART0_PORT PIOA_BASE
217 #define USART1_PORT PIOA_BASE
219 #define UART0_PERIPH PIO_PERIPH_A
220 #define UART1_PERIPH PIO_PERIPH_A
221 #define USART0_PERIPH PIO_PERIPH_A
222 #define USART1_PERIPH PIO_PERIPH_A
259 #define TWI0_PORT PIOA_BASE
260 #define TWI1_PORT PIOA_BASE
262 #define TWI0_PERIPH PIO_PERIPH_A
263 #define TWI1_PERIPH PIO_PERIPH_A
269 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
270 #define TWI0_PORT PIOA_BASE
271 #define TWI1_PORT PIOB_BASE
273 #define TWI0_PERIPH PIO_PERIPH_A
274 #define TWI1_PERIPH PIO_PERIPH_A
281 #define TWI0_PORT PIOA_BASE
282 #define TWI1_PORT PIOA_BASE
284 #define TWI0_PERIPH PIO_PERIPH_A
285 #define TWI1_PERIPH PIO_PERIPH_A
294 #define SSC_PORT PIOA_BASE
295 #define SSC_PIO_PDR PIOA_PDR
296 #define SSC_RECV_PERIPH PIO_PERIPH_A
297 #define SSC_TRAN_PERIPH PIO_PERIPH_B
305 #define SSC_PORT /* None! */
306 #define SSC_PIO_PDR /* None! */
307 #define SSC_RECV_PERIPH /* None! */
308 #define SSC_TRAN_PERIPH /* None! */
309 #define SSC_RD /* None! */
310 #define SSC_RF /* None! */
311 #define SSC_RK /* None! */
312 #define SSC_TD /* None! */
313 #define SSC_TF /* None! */
314 #define SSC_TK /* None! */
316 #define SSC_PORT PIOA_BASE
317 #define SSC_PIO_PDR PIOA_PDR
318 #define SSC_RECV_PERIPH PIO_PERIPH_A
319 #define SSC_TRAN_PERIPH PIO_PERIPH_A
327 #define SSC_PORT PIOA_BASE
328 #define SSC_PIO_PDR PIOA_PDR
329 #define SSC_RECV_PERIPH PIO_PERIPH_A
330 #define SSC_TRAN_PERIPH PIO_PERIPH_A
338 #error no ssc pins are defined for this cpu