4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \author Daniele Basile <asterix@develer.com>
35 * SAM3 Analog to Digital Converter.
43 /** ADC registers base. */
44 #define ADC_BASE 0x400C0000
47 * ADC control register
50 #define ADC_CR_OFF 0x00000000 ///< Control register offeset.
51 #define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address.
52 #define ADC_SWRST 0 ///< Software reset.
53 #define ADC_START 1 ///< Start conversion.
60 #define ADC_MR_OFF 0x00000004 ///< Mode register offeset.
61 #define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address.
62 #define ADC_TRGEN 0 ///< Trigger enable.
64 #define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0.
65 #define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1.
66 #define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2.
67 #define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0.
68 #define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1.
70 #define ADC_LOWRES 4 ///< Resolution 0: 12-bit, 1: 10-bit.
71 #define ADC_SLEEP 5 ///< Sleep mode.
75 * Prescaler rate selection.
76 * ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2)
78 #define ADC_PRESCALER_MASK 0x0000FF00 ///< Prescaler rate selection mask.
79 #define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift.
84 #define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask.
85 #define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
86 #define ADC_SUT0 0 ///< 0 period of ADCClock.
87 #define ADC_SUT1 1 ///< 8 period of ADCClock.
88 #define ADC_SUT2 2 ///< 16 period of ADCClock.
89 #define ADC_SUT3 3 ///< 24 period of ADCClock.
90 #define ADC_SUT4 4 ///< 64 period of ADCClock.
91 #define ADC_SUT5 5 ///< 80 period of ADCClock.
92 #define ADC_SUT6 6 ///< 96 period of ADCClock.
93 #define ADC_SUT7 7 ///< 112 period of ADCClock.
94 #define ADC_SUT8 8 ///< 512 period of ADCClock.
95 #define ADC_SUT9 9 ///< 576 period of ADCClock.
96 #define ADC_SUT10 10 ///< 640 period of ADCClock.
97 #define ADC_SUT11 11 ///< 704 period of ADCClock.
98 #define ADC_SUT12 12 ///< 768 period of ADCClock.
99 #define ADC_SUT13 13 ///< 832 period of ADCClock.
100 #define ADC_SUT14 14 ///< 832 period of ADCClock.
101 #define ADC_SUT15 15 ///< 896 period of ADCClock.
102 #define ADC_SUT16 16 ///< 960 period of ADCClock.
106 * Sample & hold time.
108 #define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask.
109 #define ADC_SHTIME_SHIFT 20 ///< Sample & hold time shift.
110 #define ADC_AST3 0 ///< 3 period of ADCClock
111 #define ADC_AST5 1 ///< 5 period of ADCClock
112 #define ADC_AST9 2 ///< 9 period of ADCClock
113 #define ADC_AST17 3 ///< 17 period of ADCClock
117 * ADC channel enable register
119 #define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
120 #define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address.
123 * ADC channel disable register
125 #define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
126 #define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address.
129 * ADC channel status register
131 #define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
132 #define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address.
134 #define ADC_CH_MASK 0x000000FF ///< Channel mask.
135 #define ADC_CH0 0 ///< Channel 0
136 #define ADC_CH1 1 ///< Channel 1
137 #define ADC_CH2 2 ///< Channel 2
138 #define ADC_CH3 3 ///< Channel 3
139 #define ADC_CH4 4 ///< Channel 4
140 #define ADC_CH5 5 ///< Channel 5
141 #define ADC_CH6 6 ///< Channel 6
142 #define ADC_CH7 7 ///< Channel 7
145 * ADC Interrupt enable register.
147 #define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
148 #define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register.
151 * ADC Interrupt disable register.
153 #define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
154 #define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register.
157 * ADC Interrupt mask register.
159 #define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset.
160 #define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register.
163 * ADC Interrupt status register.
165 #define ADC_ISR_OFF 0x00000030 ///< Interrupt status register offeset.
166 #define ADC_ISR (*((reg32_t *)(ADC_BASE + ADC_ISR_OFF))) ///< Interrupt status register.
168 #define ADC_EOC_MASK 0x000000FF ///< End of converison mask.
169 #define ADC_EOC0 0 ///< End of conversion channel 0.
170 #define ADC_EOC1 1 ///< End of conversion channel 1.
171 #define ADC_EOC2 2 ///< End of conversion channel 2.
172 #define ADC_EOC3 3 ///< End of conversion channel 3.
173 #define ADC_EOC4 4 ///< End of conversion channel 4.
174 #define ADC_EOC5 5 ///< End of conversion channel 5.
175 #define ADC_EOC6 6 ///< End of conversion channel 6.
176 #define ADC_EOC7 7 ///< End of conversion channel 7.
178 #define ADC_OVRE0 8 ///< Overrun error channel 0.
179 #define ADC_OVRE1 9 ///< Overrun error channel 1.
180 #define ADC_OVRE2 10 ///< Overrun error channel 2.
181 #define ADC_OVRE3 11 ///< Overrun error channel 3.
182 #define ADC_OVRE4 12 ///< Overrun error channel 4.
183 #define ADC_OVRE5 13 ///< Overrun error channel 5.
184 #define ADC_OVRE6 14 ///< Overrun error channel 6.
185 #define ADC_OVRE7 15 ///< Overrun error channel 7.
187 #define ADC_DRDY 24 ///< Data ready.
188 #define ADC_GOVRE 25 ///< General overrun error.
189 #define ADC_COMPE 26 ///< Comparition event interrupt mask.
190 #define ADC_ENDRX 27 ///< End of RX buffer.
191 #define ADC_RXBUFF 28 ///< Rx buffer full.
194 * ADC last convert data register.
196 #define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset.
197 #define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted RAW data register.
198 #define ADC_LDATA (ADC_LCDR & 0xFFF) ///< Last data converted register.
199 #define ADC_CHNB ((ADC_LCDR & 0xF000) >> 12) ///< Channel number.
201 #endif /* SAM3_ADC_H */