4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \author Daniele Basile <asterix@develer.com>
35 * SAM3X DMAC register definitions.
41 /** DMAC registers base. */
42 #define DMAC_BASE 0x400C4000
44 #define DMAC_GCFG (*((reg32_t *)(DMAC_BASE + 0x000))) ///< Global Configuration Register.
45 #define DMAC_EN (*((reg32_t *)(DMAC_BASE + 0x004))) ///< Enable Register.
46 #define DMAC_SREQ (*((reg32_t *)(DMAC_BASE + 0x008))) ///< Software Single Request Register.
47 #define DMAC_CREQ (*((reg32_t *)(DMAC_BASE + 0x00C))) ///< Software Chunk Transfer Request Register.
48 #define DMAC_LAST (*((reg32_t *)(DMAC_BASE + 0x010))) ///< Software Last Transfer Flag Register.
49 #define DMAC_EBCIER (*((reg32_t *)(DMAC_BASE + 0x018))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
50 #define DMAC_EBCIDR (*((reg32_t *)(DMAC_BASE + 0x01C))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.
51 #define DMAC_EBCIMR (*((reg32_t *)(DMAC_BASE + 0x020))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.
52 #define DMAC_EBCISR (*((reg32_t *)(DMAC_BASE + 0x024))) ///< Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.
53 #define DMAC_CHER (*((reg32_t *)(DMAC_BASE + 0x028))) ///< Channel Handler Enable Register.
54 #define DMAC_CHDR (*((reg32_t *)(DMAC_BASE + 0x02C))) ///< Channel Handler Disable Register.
55 #define DMAC_CHSR (*((reg32_t *)(DMAC_BASE + 0x030))) ///< Channel Handler Status Register.
56 #define DMAC_SADDR0 (*((reg32_t *)(DMAC_BASE + 0x03C))) ///< Channel Source Address Register (ch_num = 0).
57 #define DMAC_DADDR0 (*((reg32_t *)(DMAC_BASE + 0x040))) ///< Channel Destination Address Register (ch_num = 0).
58 #define DMAC_DSCR0 (*((reg32_t *)(DMAC_BASE + 0x044))) ///< Channel Descriptor Address Register (ch_num = 0).
59 #define DMAC_CTRLA0 (*((reg32_t *)(DMAC_BASE + 0x048))) ///< Channel Control A Register (ch_num = 0).
60 #define DMAC_CTRLB0 (*((reg32_t *)(DMAC_BASE + 0x04C))) ///< Channel Control B Register (ch_num = 0).
61 #define DMAC_CFG0 (*((reg32_t *)(DMAC_BASE + 0x050))) ///< Channel Configuration Register (ch_num = 0).
62 #define DMAC_SADDR1 (*((reg32_t *)(DMAC_BASE + 0x064))) ///< Channel Source Address Register (ch_num = 1).
63 #define DMAC_DADDR1 (*((reg32_t *)(DMAC_BASE + 0x068))) ///< Channel Destination Address Register (ch_num = 1).
64 #define DMAC_DSCR1 (*((reg32_t *)(DMAC_BASE + 0x06C))) ///< Channel Descriptor Address Register (ch_num = 1).
65 #define DMAC_CTRLA1 (*((reg32_t *)(DMAC_BASE + 0x070))) ///< Channel Control A Register (ch_num = 1).
66 #define DMAC_CTRLB1 (*((reg32_t *)(DMAC_BASE + 0x074))) ///< Channel Control B Register (ch_num = 1).
67 #define DMAC_CFG1 (*((reg32_t *)(DMAC_BASE + 0x078))) ///< Channel Configuration Register (ch_num = 1).
68 #define DMAC_SADDR2 (*((reg32_t *)(DMAC_BASE + 0x08C))) ///< Channel Source Address Register (ch_num = 2).
69 #define DMAC_DADDR2 (*((reg32_t *)(DMAC_BASE + 0x090))) ///< Channel Destination Address Register (ch_num = 2).
70 #define DMAC_DSCR2 (*((reg32_t *)(DMAC_BASE + 0x094))) ///< Channel Descriptor Address Register (ch_num = 2).
71 #define DMAC_CTRLA2 (*((reg32_t *)(DMAC_BASE + 0x098))) ///< Channel Control A Register (ch_num = 2).
72 #define DMAC_CTRLB2 (*((reg32_t *)(DMAC_BASE + 0x09C))) ///< Channel Control B Register (ch_num = 2).
73 #define DMAC_CFG2 (*((reg32_t *)(DMAC_BASE + 0x0A0))) ///< Channel Configuration Register (ch_num = 2).
74 #define DMAC_SADDR3 (*((reg32_t *)(DMAC_BASE + 0x0B4))) ///< Channel Source Address Register (ch_num = 3).
75 #define DMAC_DADDR3 (*((reg32_t *)(DMAC_BASE + 0x0B8))) ///< Channel Destination Address Register (ch_num = 3).
76 #define DMAC_DSCR3 (*((reg32_t *)(DMAC_BASE + 0x0BC))) ///< Channel Descriptor Address Register (ch_num = 3).
77 #define DMAC_CTRLA3 (*((reg32_t *)(DMAC_BASE + 0x0C0))) ///< Channel Control A Register (ch_num = 3).
78 #define DMAC_CTRLB3 (*((reg32_t *)(DMAC_BASE + 0x0C4))) ///< Channel Control B Register (ch_num = 3).
79 #define DMAC_CFG3 (*((reg32_t *)(DMAC_BASE + 0x0C8))) ///< Channel Configuration Register (ch_num = 3).
80 #define DMAC_SADDR4 (*((reg32_t *)(DMAC_BASE + 0x0DC))) ///< Channel Source Address Register (ch_num = 4).
81 #define DMAC_DADDR4 (*((reg32_t *)(DMAC_BASE + 0x0E0))) ///< Channel Destination Address Register (ch_num = 4).
82 #define DMAC_DSCR4 (*((reg32_t *)(DMAC_BASE + 0x0E4))) ///< Channel Descriptor Address Register (ch_num = 4).
83 #define DMAC_CTRLA4 (*((reg32_t *)(DMAC_BASE + 0x0E8))) ///< Channel Control A Register (ch_num = 4).
84 #define DMAC_CTRLB4 (*((reg32_t *)(DMAC_BASE + 0x0EC))) ///< Channel Control B Register (ch_num = 4).
85 #define DMAC_CFG4 (*((reg32_t *)(DMAC_BASE + 0x0F0))) ///< Channel Configuration Register (ch_num = 4).
86 #define DMAC_SADDR5 (*((reg32_t *)(DMAC_BASE + 0x104))) ///< Channel Source Address Register (ch_num = 5).
87 #define DMAC_DADDR5 (*((reg32_t *)(DMAC_BASE + 0x108))) ///< Channel Destination Address Register (ch_num = 5).
88 #define DMAC_DSCR5 (*((reg32_t *)(DMAC_BASE + 0x10C))) ///< Channel Descriptor Address Register (ch_num = 5).
89 #define DMAC_CTRLA5 (*((reg32_t *)(DMAC_BASE + 0x110))) ///< Channel Control A Register (ch_num = 5).
90 #define DMAC_CTRLB5 (*((reg32_t *)(DMAC_BASE + 0x114))) ///< Channel Control B Register (ch_num = 5).
91 #define DMAC_CFG5 (*((reg32_t *)(DMAC_BASE + 0x118))) ///< Channel Configuration Register (ch_num = 5).
92 #define DMAC_WPMR (*((reg32_t *)(DMAC_BASE + 0x1E4))) ///< Write Protect Mode Register.
93 #define DMAC_WPSR (*((reg32_t *)(DMAC_BASE + 0x1E8))) ///< Write Protect Status Register.
99 * DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register
101 #define DMAC_GCFG_ARB_CFG 4 ///< (DMAC_GCFG) Arbiter Configuration.
104 * DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register
106 #define DMAC_EN_ENABLE 0 ///< (DMAC_EN).
109 * DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register
111 #define DMAC_SREQ_SSREQ0 0 ///< (DMAC_SREQ) Source Request.
112 #define DMAC_SREQ_DSREQ0 1 ///< (DMAC_SREQ) Destination Request.
113 #define DMAC_SREQ_SSREQ1 2 ///< (DMAC_SREQ) Source Request.
114 #define DMAC_SREQ_DSREQ1 3 ///< (DMAC_SREQ) Destination Request.
115 #define DMAC_SREQ_SSREQ2 4 ///< (DMAC_SREQ) Source Request.
116 #define DMAC_SREQ_DSREQ2 5 ///< (DMAC_SREQ) Destination Request.
117 #define DMAC_SREQ_SSREQ3 6 ///< (DMAC_SREQ) Source Request.
118 #define DMAC_SREQ_DSREQ3 7 ///< (DMAC_SREQ) Destination Request.
119 #define DMAC_SREQ_SSREQ4 8 ///< (DMAC_SREQ) Source Request.
120 #define DMAC_SREQ_DSREQ4 9 ///< (DMAC_SREQ) Destination Request.
121 #define DMAC_SREQ_SSREQ5 10 ///< (DMAC_SREQ) Source Request.
122 #define DMAC_SREQ_DSREQ5 11 ///< (DMAC_SREQ) Destination Request.
125 * DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register
127 #define DMAC_CREQ_SCREQ0 0 ///< (DMAC_CREQ) Source Chunk Request.
128 #define DMAC_CREQ_DCREQ0 1 ///< (DMAC_CREQ) Destination Chunk Request.
129 #define DMAC_CREQ_SCREQ1 2 ///< (DMAC_CREQ) Source Chunk Request.
130 #define DMAC_CREQ_DCREQ1 3 ///< (DMAC_CREQ) Destination Chunk Request.
131 #define DMAC_CREQ_SCREQ2 4 ///< (DMAC_CREQ) Source Chunk Request.
132 #define DMAC_CREQ_DCREQ2 5 ///< (DMAC_CREQ) Destination Chunk Request.
133 #define DMAC_CREQ_SCREQ3 6 ///< (DMAC_CREQ) Source Chunk Request.
134 #define DMAC_CREQ_DCREQ3 7 ///< (DMAC_CREQ) Destination Chunk Request.
135 #define DMAC_CREQ_SCREQ4 8 ///< (DMAC_CREQ) Source Chunk Request.
136 #define DMAC_CREQ_DCREQ4 9 ///< (DMAC_CREQ) Destination Chunk Request.
137 #define DMAC_CREQ_SCREQ5 10 ///< (DMAC_CREQ) Source Chunk Request.
138 #define DMAC_CREQ_DCREQ5 11 ///< (DMAC_CREQ) Destination Chunk Request.
141 * DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register
143 #define DMAC_LAST_SLAST0 0 ///< (DMAC_LAST) Source Last.
144 #define DMAC_LAST_DLAST0 1 ///< (DMAC_LAST) Destination Last.
145 #define DMAC_LAST_SLAST1 2 ///< (DMAC_LAST) Source Last.
146 #define DMAC_LAST_DLAST1 3 ///< (DMAC_LAST) Destination Last.
147 #define DMAC_LAST_SLAST2 4 ///< (DMAC_LAST) Source Last.
148 #define DMAC_LAST_DLAST2 5 ///< (DMAC_LAST) Destination Last.
149 #define DMAC_LAST_SLAST3 6 ///< (DMAC_LAST) Source Last.
150 #define DMAC_LAST_DLAST3 7 ///< (DMAC_LAST) Destination Last.
151 #define DMAC_LAST_SLAST4 8 ///< (DMAC_LAST) Source Last.
152 #define DMAC_LAST_DLAST4 9 ///< (DMAC_LAST) Destination Last.
153 #define DMAC_LAST_SLAST5 10 ///< (DMAC_LAST) Source Last.
154 #define DMAC_LAST_DLAST5 11 ///< (DMAC_LAST) Destination Last.
157 * DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error,
158 * Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
160 #define DMAC_EBCIER_BTC0 0 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0].
161 #define DMAC_EBCIER_BTC1 1 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0].
162 #define DMAC_EBCIER_BTC2 2 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0].
163 #define DMAC_EBCIER_BTC3 3 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0].
164 #define DMAC_EBCIER_BTC4 4 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0].
165 #define DMAC_EBCIER_BTC5 5 ///< (DMAC_EBCIER) Buffer Transfer Completed [5:0].
166 #define DMAC_EBCIER_CBTC0 8 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0].
167 #define DMAC_EBCIER_CBTC1 9 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0].
168 #define DMAC_EBCIER_CBTC2 10 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0].
169 #define DMAC_EBCIER_CBTC3 11 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0].
170 #define DMAC_EBCIER_CBTC4 12 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0].
171 #define DMAC_EBCIER_CBTC5 13 ///< (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0].
172 #define DMAC_EBCIER_ERR0 16 ///< (DMAC_EBCIER) Access Error [5:0].
173 #define DMAC_EBCIER_ERR1 17 ///< (DMAC_EBCIER) Access Error [5:0].
174 #define DMAC_EBCIER_ERR2 18 ///< (DMAC_EBCIER) Access Error [5:0].
175 #define DMAC_EBCIER_ERR3 19 ///< (DMAC_EBCIER) Access Error [5:0].
176 #define DMAC_EBCIER_ERR4 20 ///< (DMAC_EBCIER) Access Error [5:0].
177 #define DMAC_EBCIER_ERR5 21 ///< (DMAC_EBCIER) Access Error [5:0].
179 /* DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.*/
180 #define DMAC_EBCIDR_BTC0 0 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0].
181 #define DMAC_EBCIDR_BTC1 1 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0].
182 #define DMAC_EBCIDR_BTC2 2 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0].
183 #define DMAC_EBCIDR_BTC3 3 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0].
184 #define DMAC_EBCIDR_BTC4 4 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0].
185 #define DMAC_EBCIDR_BTC5 5 ///< (DMAC_EBCIDR) Buffer Transfer Completed [5:0].
186 #define DMAC_EBCIDR_CBTC0 8 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0].
187 #define DMAC_EBCIDR_CBTC1 9 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0].
188 #define DMAC_EBCIDR_CBTC2 10 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0].
189 #define DMAC_EBCIDR_CBTC3 11 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0].
190 #define DMAC_EBCIDR_CBTC4 12 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0].
191 #define DMAC_EBCIDR_CBTC5 13 ///< (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0].
192 #define DMAC_EBCIDR_ERR0 16 ///< (DMAC_EBCIDR) Access Error [5:0].
193 #define DMAC_EBCIDR_ERR1 17 ///< (DMAC_EBCIDR) Access Error [5:0].
194 #define DMAC_EBCIDR_ERR2 18 ///< (DMAC_EBCIDR) Access Error [5:0].
195 #define DMAC_EBCIDR_ERR3 19 ///< (DMAC_EBCIDR) Access Error [5:0].
196 #define DMAC_EBCIDR_ERR4 20 ///< (DMAC_EBCIDR) Access Error [5:0].
197 #define DMAC_EBCIDR_ERR5 21 ///< (DMAC_EBCIDR) Access Error [5:0].
199 /* DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.*/
200 #define DMAC_EBCIMR_BTC0 0 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0].
201 #define DMAC_EBCIMR_BTC1 1 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0].
202 #define DMAC_EBCIMR_BTC2 2 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0].
203 #define DMAC_EBCIMR_BTC3 3 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0].
204 #define DMAC_EBCIMR_BTC4 4 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0].
205 #define DMAC_EBCIMR_BTC5 5 ///< (DMAC_EBCIMR) Buffer Transfer Completed [5:0].
206 #define DMAC_EBCIMR_CBTC0 8 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0].
207 #define DMAC_EBCIMR_CBTC1 9 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0].
208 #define DMAC_EBCIMR_CBTC2 10 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0].
209 #define DMAC_EBCIMR_CBTC3 11 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0].
210 #define DMAC_EBCIMR_CBTC4 12 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0].
211 #define DMAC_EBCIMR_CBTC5 13 ///< (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0].
212 #define DMAC_EBCIMR_ERR0 16 ///< (DMAC_EBCIMR) Access Error [5:0].
213 #define DMAC_EBCIMR_ERR1 17 ///< (DMAC_EBCIMR) Access Error [5:0].
214 #define DMAC_EBCIMR_ERR2 18 ///< (DMAC_EBCIMR) Access Error [5:0].
215 #define DMAC_EBCIMR_ERR3 19 ///< (DMAC_EBCIMR) Access Error [5:0].
216 #define DMAC_EBCIMR_ERR4 20 ///< (DMAC_EBCIMR) Access Error [5:0].
217 #define DMAC_EBCIMR_ERR5 21 ///< (DMAC_EBCIMR) Access Error [5:0].
219 /* DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.*/
220 #define DMAC_EBCISR_BTC0 0 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0].
221 #define DMAC_EBCISR_BTC1 1 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0].
222 #define DMAC_EBCISR_BTC2 2 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0].
223 #define DMAC_EBCISR_BTC3 3 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0].
224 #define DMAC_EBCISR_BTC4 4 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0].
225 #define DMAC_EBCISR_BTC5 5 ///< (DMAC_EBCISR) Buffer Transfer Completed [5:0].
226 #define DMAC_EBCISR_CBTC0 8 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0].
227 #define DMAC_EBCISR_CBTC1 9 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0].
228 #define DMAC_EBCISR_CBTC2 10 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0].
229 #define DMAC_EBCISR_CBTC3 11 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0].
230 #define DMAC_EBCISR_CBTC4 12 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0].
231 #define DMAC_EBCISR_CBTC5 13 ///< (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0].
232 #define DMAC_EBCISR_ERR0 16 ///< (DMAC_EBCISR) Access Error [5:0].
233 #define DMAC_EBCISR_ERR1 17 ///< (DMAC_EBCISR) Access Error [5:0].
234 #define DMAC_EBCISR_ERR2 18 ///< (DMAC_EBCISR) Access Error [5:0].
235 #define DMAC_EBCISR_ERR3 19 ///< (DMAC_EBCISR) Access Error [5:0].
236 #define DMAC_EBCISR_ERR4 20 ///< (DMAC_EBCISR) Access Error [5:0].
237 #define DMAC_EBCISR_ERR5 21 ///< (DMAC_EBCISR) Access Error [5:0].
239 /* DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register*/
240 #define DMAC_CHER_ENA0 0 ///< (DMAC_CHER) Enable [5:0].
241 #define DMAC_CHER_ENA1 1 ///< (DMAC_CHER) Enable [5:0].
242 #define DMAC_CHER_ENA2 2 ///< (DMAC_CHER) Enable [5:0].
243 #define DMAC_CHER_ENA3 3 ///< (DMAC_CHER) Enable [5:0].
244 #define DMAC_CHER_ENA4 4 ///< (DMAC_CHER) Enable [5:0].
245 #define DMAC_CHER_ENA5 5 ///< (DMAC_CHER) Enable [5:0].
246 #define DMAC_CHER_SUSP0 8 ///< (DMAC_CHER) Suspend [5:0].
247 #define DMAC_CHER_SUSP1 9 ///< (DMAC_CHER) Suspend [5:0].
248 #define DMAC_CHER_SUSP2 10 ///< (DMAC_CHER) Suspend [5:0].
249 #define DMAC_CHER_SUSP3 11 ///< (DMAC_CHER) Suspend [5:0].
250 #define DMAC_CHER_SUSP4 12 ///< (DMAC_CHER) Suspend [5:0].
251 #define DMAC_CHER_SUSP5 13 ///< (DMAC_CHER) Suspend [5:0].
252 #define DMAC_CHER_KEEP0 24 ///< (DMAC_CHER) Keep on [5:0].
253 #define DMAC_CHER_KEEP1 25 ///< (DMAC_CHER) Keep on [5:0].
254 #define DMAC_CHER_KEEP2 26 ///< (DMAC_CHER) Keep on [5:0].
255 #define DMAC_CHER_KEEP3 27 ///< (DMAC_CHER) Keep on [5:0].
256 #define DMAC_CHER_KEEP4 28 ///< (DMAC_CHER) Keep on [5:0].
257 #define DMAC_CHER_KEEP5 29 ///< (DMAC_CHER) Keep on [5:0].
259 /* DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register*/
260 #define DMAC_CHDR_DIS0 0 ///< (DMAC_CHDR) Disable [5:0].
261 #define DMAC_CHDR_DIS1 1 ///< (DMAC_CHDR) Disable [5:0].
262 #define DMAC_CHDR_DIS2 2 ///< (DMAC_CHDR) Disable [5:0].
263 #define DMAC_CHDR_DIS3 3 ///< (DMAC_CHDR) Disable [5:0].
264 #define DMAC_CHDR_DIS4 4 ///< (DMAC_CHDR) Disable [5:0].
265 #define DMAC_CHDR_DIS5 5 ///< (DMAC_CHDR) Disable [5:0].
266 #define DMAC_CHDR_RES0 8 ///< (DMAC_CHDR) Resume [5:0].
267 #define DMAC_CHDR_RES1 9 ///< (DMAC_CHDR) Resume [5:0].
268 #define DMAC_CHDR_RES2 10 ///< (DMAC_CHDR) Resume [5:0].
269 #define DMAC_CHDR_RES3 11 ///< (DMAC_CHDR) Resume [5:0].
270 #define DMAC_CHDR_RES4 12 ///< (DMAC_CHDR) Resume [5:0].
271 #define DMAC_CHDR_RES5 13 ///< (DMAC_CHDR) Resume [5:0].
273 /* DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register*/
274 #define DMAC_CHSR_EN_MASK 0x31 ///<
275 #define DMAC_CHSR_ENA0 0 ///< (DMAC_CHSR) Enable [5:0].
276 #define DMAC_CHSR_ENA1 1 ///< (DMAC_CHSR) Enable [5:0].
277 #define DMAC_CHSR_ENA2 2 ///< (DMAC_CHSR) Enable [5:0].
278 #define DMAC_CHSR_ENA3 3 ///< (DMAC_CHSR) Enable [5:0].
279 #define DMAC_CHSR_ENA4 4 ///< (DMAC_CHSR) Enable [5:0].
280 #define DMAC_CHSR_ENA5 5 ///< (DMAC_CHSR) Enable [5:0].
281 #define DMAC_CHSR_SUSP0 8 ///< (DMAC_CHSR) Suspend [5:0].
282 #define DMAC_CHSR_SUSP1 9 ///< (DMAC_CHSR) Suspend [5:0].
283 #define DMAC_CHSR_SUSP2 10 ///< (DMAC_CHSR) Suspend [5:0].
284 #define DMAC_CHSR_SUSP3 11 ///< (DMAC_CHSR) Suspend [5:0].
285 #define DMAC_CHSR_SUSP4 12 ///< (DMAC_CHSR) Suspend [5:0].
286 #define DMAC_CHSR_SUSP5 13 ///< (DMAC_CHSR) Suspend [5:0].
287 #define DMAC_CHSR_EMPT0 16 ///< (DMAC_CHSR) Empty [5:0].
288 #define DMAC_CHSR_EMPT1 17 ///< (DMAC_CHSR) Empty [5:0].
289 #define DMAC_CHSR_EMPT2 18 ///< (DMAC_CHSR) Empty [5:0].
290 #define DMAC_CHSR_EMPT3 19 ///< (DMAC_CHSR) Empty [5:0].
291 #define DMAC_CHSR_EMPT4 20 ///< (DMAC_CHSR) Empty [5:0].
292 #define DMAC_CHSR_EMPT5 21 ///< (DMAC_CHSR) Empty [5:0].
293 #define DMAC_CHSR_STAL0 24 ///< (DMAC_CHSR) Stalled [5:0].
294 #define DMAC_CHSR_STAL1 25 ///< (DMAC_CHSR) Stalled [5:0].
295 #define DMAC_CHSR_STAL2 26 ///< (DMAC_CHSR) Stalled [5:0].
296 #define DMAC_CHSR_STAL3 27 ///< (DMAC_CHSR) Stalled [5:0].
297 #define DMAC_CHSR_STAL4 28 ///< (DMAC_CHSR) Stalled [5:0].
298 #define DMAC_CHSR_STAL5 29 ///< (DMAC_CHSR) Stalled [5:0].
300 /* DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register*/
301 #define DMAC_CTRLA_BTSIZE_MASK 0xffff ///< (DMAC_CTRLA) Buffer Transfer Size.
302 #define DMAC_CTRLA_SCSIZE_MASK 0x70000 ///< (DMAC_CTRLA) Source Chunk Transfer Size..
303 #define DMAC_CTRLA_SCSIZE_CHK_1 0x00000 ///< (DMAC_CTRLA) 1 data transferred.
304 #define DMAC_CTRLA_SCSIZE_CHK_4 0x10000 ///< (DMAC_CTRLA) 4 data transferred.
305 #define DMAC_CTRLA_SCSIZE_CHK_8 0x20000 ///< (DMAC_CTRLA) 8 data transferred.
306 #define DMAC_CTRLA_SCSIZE_CHK_16 0x30000 ///< (DMAC_CTRLA) 16 data transferred.
307 #define DMAC_CTRLA_SCSIZE_CHK_32 0x40000 ///< (DMAC_CTRLA) 32 data transferred.
308 #define DMAC_CTRLA_SCSIZE_CHK_64 0x50000 ///< (DMAC_CTRLA) 64 data transferred.
309 #define DMAC_CTRLA_SCSIZE_CHK_128 0x60000 ///< (DMAC_CTRLA) 128 data transferred.
310 #define DMAC_CTRLA_SCSIZE_CHK_256 0x70000 ///< (DMAC_CTRLA) 256 data transferred.
311 #define DMAC_CTRLA_DCSIZE_MASK 0x700000 ///< (DMAC_CTRLA) Destination Chunk Transfer Size.
312 #define DMAC_CTRLA_DCSIZE_CHK_1 0x000000 ///< (DMAC_CTRLA) 1 data transferred.
313 #define DMAC_CTRLA_DCSIZE_CHK_4 0x100000 ///< (DMAC_CTRLA) 4 data transferred.
314 #define DMAC_CTRLA_DCSIZE_CHK_8 0x200000 ///< (DMAC_CTRLA) 8 data transferred.
315 #define DMAC_CTRLA_DCSIZE_CHK_16 0x300000 ///< (DMAC_CTRLA) 16 data transferred.
316 #define DMAC_CTRLA_DCSIZE_CHK_32 0x400000 ///< (DMAC_CTRLA) 32 data transferred.
317 #define DMAC_CTRLA_DCSIZE_CHK_64 0x500000 ///< (DMAC_CTRLA) 64 data transferred.
318 #define DMAC_CTRLA_DCSIZE_CHK_128 0x600000 ///< (DMAC_CTRLA) 128 data transferred.
319 #define DMAC_CTRLA_DCSIZE_CHK_256 0x700000 ///< (DMAC_CTRLA) 256 data transferred.
320 #define DMAC_CTRLA_SRC_WIDTH_MASK 0x3000000 ///< (DMAC_CTRLA) Transfer Width for the Source.
321 #define DMAC_CTRLA_SRC_WIDTH_BYTE 0x0000000 ///< (DMAC_CTRLA) the transfer size is set to 8-bit width.
322 #define DMAC_CTRLA_SRC_WIDTH_HALF_WORD 0x1000000///< (DMAC_CTRLA) the transfer size is set to 16-bit width.
323 #define DMAC_CTRLA_SRC_WIDTH_WORD 0x2000000 ///< (DMAC_CTRLA) the transfer size is set to 32-bit width.
324 #define DMAC_CTRLA_DST_WIDTH_MASK 0x30000000 ///< (DMAC_CTRLA) Transfer Width for the Destination.
325 #define DMAC_CTRLA_DST_WIDTH_BYTE 0x00000000 ///< (DMAC_CTRLA) the transfer size is set to 8-bit width.
326 #define DMAC_CTRLA_DST_WIDTH_HALF_WORD 0x10000000///< (DMAC_CTRLA) the transfer size is set to 16-bit width.
327 #define DMAC_CTRLA_DST_WIDTH_WORD 0x20000000 ///< (DMAC_CTRLA) the transfer size is set to 32-bit width.
328 #define DMAC_CTRLA_DONE 31 ///< (DMAC_CTRLA) .
330 /* DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register*/
331 #define DMAC_CTRLB_SRC_DSCR 16 ///< (DMAC_CTRLB) Source Address Descriptor.
332 #define DMAC_CTRLB_DST_DSCR 20 ///< (DMAC_CTRLB) Destination Address Descriptor.
333 #define DMAC_CTRLB_FC_MASK 0xE00000 ///< (DMAC_CTRLB) Flow Control.
334 #define DMAC_CTRLB_FC_MEM2MEM_DMA_FC 0 ///< (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller.
335 #define DMAC_CTRLB_FC_MEM2PER_DMA_FC 0x200000 ///< (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller.
336 #define DMAC_CTRLB_FC_PER2MEM_DMA_FC 0x400000 ///< (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller.
337 #define DMAC_CTRLB_FC_PER2PER_DMA_FC 0x600000 ///< (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller.
338 #define DMAC_CTRLB_SRC_INCR_MASK 0x3000000 ///< (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source.
339 #define DMAC_CTRLB_SRC_INCR_INCREMENTING 0 ///< (DMAC_CTRLB) The source address is incremented.
340 #define DMAC_CTRLB_SRC_INCR_DECREMENTING 0x1000000 ///< (DMAC_CTRLB) The source address is decremented.
341 #define DMAC_CTRLB_SRC_INCR_FIXED 0x2000000 ///< (DMAC_CTRLB) The source address remains unchanged.
342 #define DMAC_CTRLB_DST_INCR_MASK 0x30000000 ///< (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination.
343 #define DMAC_CTRLB_DST_INCR_INCREMENTING 0 ///< (DMAC_CTRLB) The destination address is incremented.
344 #define DMAC_CTRLB_DST_INCR_DECREMENTING 0x10000000 ///< (DMAC_CTRLB) The destination address is decremented.
345 #define DMAC_CTRLB_DST_INCR_FIXED 0x20000000 ///< (DMAC_CTRLB) The destination address remains unchanged.
346 #define DMAC_CTRLB_IEN 30 ///< (DMAC_CTRLB).
348 /* DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register*/
349 #define DMAC_CFG_SRC_PER_MASK 0xf ///< (DMAC_CFG) Source with Peripheral identifier.
350 #define DMAC_CFG_DST_PER_MASK 0xf0 ///< (DMAC_CFG) Destination with Peripheral identifier.
351 #define DMAC_CFG_DST_PER_SHIFT 4 ///< (DMAC_CFG) Destination with Peripheral identifier.
352 #define DMAC_CFG_SRC_H2SEL 9 ///< (DMAC_CFG) Software or Hardware Selection for the Source.
353 #define DMAC_CFG_DST_H2SEL 13 ///< (DMAC_CFG) Software or Hardware Selection for the Destination.
354 #define DMAC_CFG_SOD 16 ///< (DMAC_CFG) Stop On Done.
355 #define DMAC_CFG_LOCK_IF 20 ///< (DMAC_CFG) Interface Lock.
356 #define DMAC_CFG_LOCK_B 21 ///< (DMAC_CFG) Bus Lock.
357 #define DMAC_CFG_LOCK_IF_L 22 ///< (DMAC_CFG) Master Interface Arbiter Lock.
358 #define DMAC_CFG_AHB_PROT_MASK 0x7000000 ///< (DMAC_CFG) AHB Protection.
359 #define DMAC_CFG_FIFOCFG_MASK 0x70000000 ///< (DMAC_CFG) FIFO Configuration.
360 #define DMAC_CFG_FIFOCFG_ALAP_CFG 0x00000000 ///< (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface..
361 #define DMAC_CFG_FIFOCFG_HALF_CFG 0x10000000 ///< (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced..
362 #define DMAC_CFG_FIFOCFG_ASAP_CFG 0x20000000 ///< (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced..
363 /* DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register*/
364 #define DMAC_WPMR_WPEN 0 ///< (DMAC_WPMR) Write Protect Enable.
365 #define DMAC_WPMR_WPKEY_MASK 0xFFFFFF00 ///< (DMAC_WPMR) Write Protect KEY.
367 /* DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register*/
368 #define DMAC_WPSR_WPVS 0 ///< (DMAC_WPSR) Write Protect Violation Status.
369 #define DMAC_WPSR_WPVSRC_MASK 0x00FFFF00 ///< (DMAC_WPSR) Write Protect Violation Source.
372 #endif /* SAM3_DMAC_H */