4 * This file is part of BeRTOS.
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief AT91SAM3 PMC hardware.
43 #define PMC_SCER_R (*((reg32_t *)0x400E0400)) ///< System Clock Enable Register
44 #define PMC_SCDR_R (*((reg32_t *)0x400E0404)) ///< System Clock Disable Register
45 #define PMC_SCSR_R (*((reg32_t *)0x400E0408)) ///< System Clock Status Register
46 #define PMC_PCER_R (*((reg32_t *)0x400E0410)) ///< Peripheral Clock Enable Register
47 #define PMC_PCDR_R (*((reg32_t *)0x400E0414)) ///< Peripheral Clock Disable Register
48 #define PMC_PCSR_R (*((reg32_t *)0x400E0418)) ///< Peripheral Clock Status Register
49 #define CKGR_MOR_R (*((reg32_t *)0x400E0420)) ///< Main Oscillator Register
50 #define CKGR_MCFR_R (*((reg32_t *)0x400E0424)) ///< Main Clock Frequency Register
51 #define CKGR_PLLR_R (*((reg32_t *)0x400E0428)) ///< PLL Register
52 #define PMC_MCKR_R (*((reg32_t *)0x400E0430)) ///< Master Clock Register
53 #define PMC_PCK_R (*((reg32_t *)0x400E0440)) ///< Programmable Clock 0 Register
54 #define PMC_IER_R (*((reg32_t *)0x400E0460)) ///< Interrupt Enable Register
55 #define PMC_IDR_R (*((reg32_t *)0x400E0464)) ///< Interrupt Disable Register
56 #define PMC_SR_R (*((reg32_t *)0x400E0468)) ///< Status Register
57 #define PMC_IMR_R (*((reg32_t *)0x400E046C)) ///< Interrupt Mask Register
58 #define PMC_FSMR_R (*((reg32_t *)0x400E0470)) ///< Fast Startup Mode Register
59 #define PMC_FSPR_R (*((reg32_t *)0x400E0474)) ///< Fast Startup Polarity Register
60 #define PMC_FOCR_R (*((reg32_t *)0x400E0478)) ///< Fault Output Clear Register
61 #define PMC_WPMR_R (*((reg32_t *)0x400E04E4)) ///< Write Protect Mode Register
62 #define PMC_WPSR_R (*((reg32_t *)0x400E04E8)) ///< Write Protect Status Register
63 #define PMC_OCR_R (*((reg32_t *)0x400E0510)) ///< Oscillator Calibration Register
67 * PMC register addresses.
70 #define PMC_SCER 0x400E0400 ///< System Clock Enable Register
71 #define PMC_SCDR 0x400E0404 ///< System Clock Disable Register
72 #define PMC_SCSR 0x400E0408 ///< System Clock Status Register
73 #define PMC_PCER 0x400E0410 ///< Peripheral Clock Enable Register
74 #define PMC_PCDR 0x400E0414 ///< Peripheral Clock Disable Register
75 #define PMC_PCSR 0x400E0418 ///< Peripheral Clock Status Register
76 #define PMC_MOR 0x400E0420 ///< Main Oscillator Register
77 #define PMC_MCFR 0x400E0424 ///< Main Clock Frequency Register
78 #define PMC_PLLR 0x400E0428 ///< PLL Register
79 #define PMC_MCKR 0x400E0430 ///< Master Clock Register
80 #define PMC_PCK 0x400E0440 ///< Programmable Clock 0 Register
81 #define PMC_IER 0x400E0460 ///< Interrupt Enable Register
82 #define PMC_IDR 0x400E0464 ///< Interrupt Disable Register
83 #define PMC_SR 0x400E0468 ///< Status Register
84 #define PMC_IMR 0x400E046C ///< Interrupt Mask Register
85 #define PMC_FSMR 0x400E0470 ///< Fast Startup Mode Register
86 #define PMC_FSPR 0x400E0474 ///< Fast Startup Polarity Register
87 #define PMC_FOCR 0x400E0478 ///< Fault Output Clear Register
88 #define PMC_WPMR 0x400E04E4 ///< Write Protect Mode Register
89 #define PMC_WPSR 0x400E04E8 ///< Write Protect Status Register
90 #define PMC_OCR 0x400E0510 ///< Oscillator Calibration Register
94 * Defines for bit fields in PMC_SCER register.
97 #define PMC_SCER_PCK0 BV(8) ///< Programmable Clock 0 Output Enable
98 #define PMC_SCER_PCK1 BV(9) ///< Programmable Clock 1 Output Enable
99 #define PMC_SCER_PCK2 BV(10) ///< Programmable Clock 2 Output Enable
103 * Defines for bit fields in PMC_SCDR register.
106 #define PMC_SCDR_PCK0 BV(8) ///< Programmable Clock 0 Output Disable
107 #define PMC_SCDR_PCK1 BV(9) ///< Programmable Clock 1 Output Disable
108 #define PMC_SCDR_PCK2 BV(10) ///< Programmable Clock 2 Output Disable
112 * Defines for bit fields in PMC_SCSR register.
115 #define PMC_SCSR_PCK0 BV(8) ///< Programmable Clock 0 Output Status
116 #define PMC_SCSR_PCK1 BV(9) ///< Programmable Clock 1 Output Status
117 #define PMC_SCSR_PCK2 BV(10) ///< Programmable Clock 2 Output Status
121 * Defines for bit fields in PMC_PCER register.
124 #define PMC_PCER_PID2 BV(2) ///< Peripheral Clock 2 Enable
125 #define PMC_PCER_PID3 BV(3) ///< Peripheral Clock 3 Enable
126 #define PMC_PCER_PID4 BV(4) ///< Peripheral Clock 4 Enable
127 #define PMC_PCER_PID5 BV(5) ///< Peripheral Clock 5 Enable
128 #define PMC_PCER_PID6 BV(6) ///< Peripheral Clock 6 Enable
129 #define PMC_PCER_PID7 BV(7) ///< Peripheral Clock 7 Enable
130 #define PMC_PCER_PID8 BV(8) ///< Peripheral Clock 8 Enable
131 #define PMC_PCER_PID9 BV(9) ///< Peripheral Clock 9 Enable
132 #define PMC_PCER_PID10 BV(10) ///< Peripheral Clock 10 Enable
133 #define PMC_PCER_PID11 BV(11) ///< Peripheral Clock 11 Enable
134 #define PMC_PCER_PID12 BV(12) ///< Peripheral Clock 12 Enable
135 #define PMC_PCER_PID13 BV(13) ///< Peripheral Clock 13 Enable
136 #define PMC_PCER_PID14 BV(14) ///< Peripheral Clock 14 Enable
137 #define PMC_PCER_PID15 BV(15) ///< Peripheral Clock 15 Enable
138 #define PMC_PCER_PID16 BV(16) ///< Peripheral Clock 16 Enable
139 #define PMC_PCER_PID17 BV(17) ///< Peripheral Clock 17 Enable
140 #define PMC_PCER_PID18 BV(18) ///< Peripheral Clock 18 Enable
141 #define PMC_PCER_PID19 BV(19) ///< Peripheral Clock 19 Enable
142 #define PMC_PCER_PID20 BV(20) ///< Peripheral Clock 20 Enable
143 #define PMC_PCER_PID21 BV(21) ///< Peripheral Clock 21 Enable
144 #define PMC_PCER_PID22 BV(22) ///< Peripheral Clock 22 Enable
145 #define PMC_PCER_PID23 BV(23) ///< Peripheral Clock 23 Enable
146 #define PMC_PCER_PID24 BV(24) ///< Peripheral Clock 24 Enable
147 #define PMC_PCER_PID25 BV(25) ///< Peripheral Clock 25 Enable
148 #define PMC_PCER_PID26 BV(26) ///< Peripheral Clock 26 Enable
149 #define PMC_PCER_PID27 BV(27) ///< Peripheral Clock 27 Enable
150 #define PMC_PCER_PID28 BV(28) ///< Peripheral Clock 28 Enable
151 #define PMC_PCER_PID29 BV(29) ///< Peripheral Clock 29 Enable
152 #define PMC_PCER_PID30 BV(30) ///< Peripheral Clock 30 Enable
153 #define PMC_PCER_PID31 BV(31) ///< Peripheral Clock 31 Enable
157 * Defines for bit fields in PMC_PCDR register.
160 #define PMC_PCDR_PID2 BV(2) ///< Peripheral Clock 2 Disable
161 #define PMC_PCDR_PID3 BV(3) ///< Peripheral Clock 3 Disable
162 #define PMC_PCDR_PID4 BV(4) ///< Peripheral Clock 4 Disable
163 #define PMC_PCDR_PID5 BV(5) ///< Peripheral Clock 5 Disable
164 #define PMC_PCDR_PID6 BV(6) ///< Peripheral Clock 6 Disable
165 #define PMC_PCDR_PID7 BV(7) ///< Peripheral Clock 7 Disable
166 #define PMC_PCDR_PID8 BV(8) ///< Peripheral Clock 8 Disable
167 #define PMC_PCDR_PID9 BV(9) ///< Peripheral Clock 9 Disable
168 #define PMC_PCDR_PID10 BV(10) ///< Peripheral Clock 10 Disable
169 #define PMC_PCDR_PID11 BV(11) ///< Peripheral Clock 11 Disable
170 #define PMC_PCDR_PID12 BV(12) ///< Peripheral Clock 12 Disable
171 #define PMC_PCDR_PID13 BV(13) ///< Peripheral Clock 13 Disable
172 #define PMC_PCDR_PID14 BV(14) ///< Peripheral Clock 14 Disable
173 #define PMC_PCDR_PID15 BV(15) ///< Peripheral Clock 15 Disable
174 #define PMC_PCDR_PID16 BV(16) ///< Peripheral Clock 16 Disable
175 #define PMC_PCDR_PID17 BV(17) ///< Peripheral Clock 17 Disable
176 #define PMC_PCDR_PID18 BV(18) ///< Peripheral Clock 18 Disable
177 #define PMC_PCDR_PID19 BV(19) ///< Peripheral Clock 19 Disable
178 #define PMC_PCDR_PID20 BV(20) ///< Peripheral Clock 20 Disable
179 #define PMC_PCDR_PID21 BV(21) ///< Peripheral Clock 21 Disable
180 #define PMC_PCDR_PID22 BV(22) ///< Peripheral Clock 22 Disable
181 #define PMC_PCDR_PID23 BV(23) ///< Peripheral Clock 23 Disable
182 #define PMC_PCDR_PID24 BV(24) ///< Peripheral Clock 24 Disable
183 #define PMC_PCDR_PID25 BV(25) ///< Peripheral Clock 25 Disable
184 #define PMC_PCDR_PID26 BV(26) ///< Peripheral Clock 26 Disable
185 #define PMC_PCDR_PID27 BV(27) ///< Peripheral Clock 27 Disable
186 #define PMC_PCDR_PID28 BV(28) ///< Peripheral Clock 28 Disable
187 #define PMC_PCDR_PID29 BV(29) ///< Peripheral Clock 29 Disable
188 #define PMC_PCDR_PID30 BV(30) ///< Peripheral Clock 30 Disable
189 #define PMC_PCDR_PID31 BV(31) ///< Peripheral Clock 31 Disable
193 * Defines for bit fields in PMC_PCSR register.
196 #define PMC_PCSR_PID2 BV(2) ///< Peripheral Clock 2 Status
197 #define PMC_PCSR_PID3 BV(3) ///< Peripheral Clock 3 Status
198 #define PMC_PCSR_PID4 BV(4) ///< Peripheral Clock 4 Status
199 #define PMC_PCSR_PID5 BV(5) ///< Peripheral Clock 5 Status
200 #define PMC_PCSR_PID6 BV(6) ///< Peripheral Clock 6 Status
201 #define PMC_PCSR_PID7 BV(7) ///< Peripheral Clock 7 Status
202 #define PMC_PCSR_PID8 BV(8) ///< Peripheral Clock 8 Status
203 #define PMC_PCSR_PID9 BV(9) ///< Peripheral Clock 9 Status
204 #define PMC_PCSR_PID10 BV(10) ///< Peripheral Clock 10 Status
205 #define PMC_PCSR_PID11 BV(11) ///< Peripheral Clock 11 Status
206 #define PMC_PCSR_PID12 BV(12) ///< Peripheral Clock 12 Status
207 #define PMC_PCSR_PID13 BV(13) ///< Peripheral Clock 13 Status
208 #define PMC_PCSR_PID14 BV(14) ///< Peripheral Clock 14 Status
209 #define PMC_PCSR_PID15 BV(15) ///< Peripheral Clock 15 Status
210 #define PMC_PCSR_PID16 BV(16) ///< Peripheral Clock 16 Status
211 #define PMC_PCSR_PID17 BV(17) ///< Peripheral Clock 17 Status
212 #define PMC_PCSR_PID18 BV(18) ///< Peripheral Clock 18 Status
213 #define PMC_PCSR_PID19 BV(19) ///< Peripheral Clock 19 Status
214 #define PMC_PCSR_PID20 BV(20) ///< Peripheral Clock 20 Status
215 #define PMC_PCSR_PID21 BV(21) ///< Peripheral Clock 21 Status
216 #define PMC_PCSR_PID22 BV(22) ///< Peripheral Clock 22 Status
217 #define PMC_PCSR_PID23 BV(23) ///< Peripheral Clock 23 Status
218 #define PMC_PCSR_PID24 BV(24) ///< Peripheral Clock 24 Status
219 #define PMC_PCSR_PID25 BV(25) ///< Peripheral Clock 25 Status
220 #define PMC_PCSR_PID26 BV(26) ///< Peripheral Clock 26 Status
221 #define PMC_PCSR_PID27 BV(27) ///< Peripheral Clock 27 Status
222 #define PMC_PCSR_PID28 BV(28) ///< Peripheral Clock 28 Status
223 #define PMC_PCSR_PID29 BV(29) ///< Peripheral Clock 29 Status
224 #define PMC_PCSR_PID30 BV(30) ///< Peripheral Clock 30 Status
225 #define PMC_PCSR_PID31 BV(31) ///< Peripheral Clock 31 Status
229 * Defines for bit fields in CKGR_MOR register.
232 #define CKGR_MOR_MOSCXTEN BV(0) ///< Main Crystal Oscillator Enable
233 #define CKGR_MOR_MOSCXTBY BV(1) ///< Main Crystal Oscillator Bypass
234 #define CKGR_MOR_WAITMODE BV(2) ///< Wait Mode Command
235 #define CKGR_MOR_MOSCRCEN BV(3) ///< Main On-Chip RC Oscillator Enable
236 #define CKGR_MOR_MOSCRCF_S 4
237 #define CKGR_MOR_MOSCRCF_M (0x7 << CKGR_MOR_MOSCRCF_S) ///< Main On-Chip RC Oscillator Frequency Selection
238 #define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_M & ((value) << CKGR_MOR_MOSCRCF_S)))
239 #define CKGR_MOR_MOSCRCF_4MHZ (0x0 << CKGR_MOR_MOSCRCF_S)
240 #define CKGR_MOR_MOSCRCF_8MHZ (0x1 << CKGR_MOR_MOSCRCF_S)
241 #define CKGR_MOR_MOSCRCF_12MHZ (0x2 << CKGR_MOR_MOSCRCF_S)
242 #define CKGR_MOR_MOSCXTST_S 8
243 #define CKGR_MOR_MOSCXTST_M (0xff << CKGR_MOR_MOSCXTST_S) ///< Main Crystal Oscillator Start-up Time
244 #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_M & ((value) << CKGR_MOR_MOSCXTST_S)))
245 #define CKGR_MOR_KEY_S 16
246 #define CKGR_MOR_KEY_M (0xffu << CKGR_MOR_KEY_S) ///< Password
247 #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_M & ((value) << CKGR_MOR_KEY_S)))
248 #define CKGR_MOR_MOSCSEL BV(24) ///< Main Oscillator Selection
249 #define CKGR_MOR_CFDEN BV(25) ///< Clock Failure Detector Enable
253 * Defines for bit fields in CKGR_MCFR register.
256 #define CKGR_MCFR_MAINF_M 0xffffu ///< Main Clock Frequency mask
257 #define CKGR_MCFR_MAINFRDY BV(16) ///< Main Clock Ready
261 * Defines for bit fields in CKGR_PLLR register.
264 #define CKGR_PLLR_DIV_M 0xff ///< Divider mask
265 #define CKGR_PLLR_DIV(value) (CKGR_PLLR_DIV_M & (value))
266 #define CKGR_PLLR_PLLCOUNT_S 8
267 #define CKGR_PLLR_PLLCOUNT_M (0x3f << CKGR_PLLR_PLLCOUNT_S) ///< PLL Counter mask
268 #define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_M & ((value) << CKGR_PLLR_PLLCOUNT_S))
269 #define CKGR_PLLR_MUL_S 16
270 #define CKGR_PLLR_MUL_M (0x7ff << CKGR_PLLR_MUL_S) ///< PLL Multiplier mask
271 #define CKGR_PLLR_MUL(value) (CKGR_PLLR_MUL_M & ((value) << CKGR_PLLR_MUL_S))
272 #define CKGR_PLLR_STUCKTO1 BV(29)
276 * Defines for bit fields in PMC_MCKR register.
279 #define PMC_MCKR_CSS_M 0x3 ///< Master Clock Source Selection mask
280 #define PMC_MCKR_CSS_SLOW_CLK 0x0 ///< Slow Clock is selected
281 #define PMC_MCKR_CSS_MAIN_CLK 0x1 ///< Main Clock is selected
282 #define PMC_MCKR_CSS_PLL_CLK 0x2 ///< PLL Clock is selected
283 #define PMC_MCKR_PRES_S 4
284 #define PMC_MCKR_PRES_M (0x7u << PMC_MCKR_PRES_S) ///< Processor Clock Prescaler mask
285 #define PMC_MCKR_PRES_CLK (0x0u << PMC_MCKR_PRES_S) ///< Selected clock
286 #define PMC_MCKR_PRES_CLK_2 (0x1u << PMC_MCKR_PRES_S) ///< Selected clock divided by 2
287 #define PMC_MCKR_PRES_CLK_4 (0x2u << PMC_MCKR_PRES_S) ///< Selected clock divided by 4
288 #define PMC_MCKR_PRES_CLK_8 (0x3u << PMC_MCKR_PRES_S) ///< Selected clock divided by 8
289 #define PMC_MCKR_PRES_CLK_16 (0x4u << PMC_MCKR_PRES_S) ///< Selected clock divided by 16
290 #define PMC_MCKR_PRES_CLK_32 (0x5u << PMC_MCKR_PRES_S) ///< Selected clock divided by 32
291 #define PMC_MCKR_PRES_CLK_64 (0x6u << PMC_MCKR_PRES_S) ///< Selected clock divided by 64
292 #define PMC_MCKR_PRES_CLK_3 (0x7u << PMC_MCKR_PRES_S) ///< Selected clock divided by 3
293 #define PMC_MCKR_PLLDIV2 BV(12) ///< PLL Divisor by 2
297 * Defines for bit fields in PMC_PCK[3] register.
300 #define PMC_PCK_CSS_M 0x7 ///< Master Clock Source Selection mask
301 #define PMC_PCK_CSS_SLOW 0x0 ///< Slow Clock is selected
302 #define PMC_PCK_CSS_MAIN 0x1 ///< Main Clock is selected
303 #define PMC_PCK_CSS_PLL 0x2 ///< PLL Clock is selected
304 #define PMC_PCK_CSS_MCK 0x4 ///< Master Clock is selected
305 #define PMC_PCK_PRES_S 4
306 #define PMC_PCK_PRES_M (0x7u << PMC_PCK_PRES_S) ///< Programmable Clock Prescaler
307 #define PMC_PCK_PRES_CLK (0x0u << PMC_PCK_PRES_S) ///< Selected clock
308 #define PMC_PCK_PRES_CLK_2 (0x1u << PMC_PCK_PRES_S) ///< Selected clock divided by 2
309 #define PMC_PCK_PRES_CLK_4 (0x2u << PMC_PCK_PRES_S) ///< Selected clock divided by 4
310 #define PMC_PCK_PRES_CLK_8 (0x3u << PMC_PCK_PRES_S) ///< Selected clock divided by 8
311 #define PMC_PCK_PRES_CLK_16 (0x4u << PMC_PCK_PRES_S) ///< Selected clock divided by 16
312 #define PMC_PCK_PRES_CLK_32 (0x5u << PMC_PCK_PRES_S) ///< Selected clock divided by 32
313 #define PMC_PCK_PRES_CLK_64 (0x6u << PMC_PCK_PRES_S) ///< Selected clock divided by 64
317 * Defines for bit fields in PMC_IER register.
320 #define PMC_IER_MOSCXTS BV(0) ///< Main Crystal Oscillator Status Interrupt Enable
321 #define PMC_IER_LOCK BV(1) ///< PLL Lock Interrupt Enable
322 #define PMC_IER_MCKRDY BV(3) ///< Master Clock Ready Interrupt Enable
323 #define PMC_IER_PCKRDY0 BV(8) ///< Programmable Clock Ready 0 Interrupt Enable
324 #define PMC_IER_PCKRDY1 BV(9) ///< Programmable Clock Ready 1 Interrupt Enable
325 #define PMC_IER_PCKRDY2 BV(10) ///< Programmable Clock Ready 2 Interrupt Enable
326 #define PMC_IER_MOSCSELS BV(16) ///< Main Oscillator Selection Status Interrupt Enable
327 #define PMC_IER_MOSCRCS BV(17) ///< Main On-Chip RC Status Interrupt Enable
328 #define PMC_IER_CFDEV BV(18) ///< Clock Failure Detector Event Interrupt Enable
332 * Defines for bit fields in PMC_IDR register.
335 #define PMC_IDR_MOSCXTS BV(0) ///< Main Crystal Oscillator Status Interrupt Disable
336 #define PMC_IDR_LOCK BV(1) ///< PLL Lock Interrupt Disable
337 #define PMC_IDR_MCKRDY BV(3) ///< Master Clock Ready Interrupt Disable
338 #define PMC_IDR_PCKRDY0 BV(8) ///< Programmable Clock Ready 0 Interrupt Disable
339 #define PMC_IDR_PCKRDY1 BV(9) ///< Programmable Clock Ready 1 Interrupt Disable
340 #define PMC_IDR_PCKRDY2 BV(10) ///< Programmable Clock Ready 2 Interrupt Disable
341 #define PMC_IDR_MOSCSELS BV(16) ///< Main Oscillator Selection Status Interrupt Disable
342 #define PMC_IDR_MOSCRCS BV(17) ///< Main On-Chip RC Status Interrupt Disable
343 #define PMC_IDR_CFDEV BV(18) ///< Clock Failure Detector Event Interrupt Disable
347 * Defines for bit fields in PMC_SR register.
350 #define PMC_SR_MOSCXTS BV(0) ///< Main XTAL Oscillator Status
351 #define PMC_SR_LOCK BV(1) ///< PLL Lock Status
352 #define PMC_SR_MCKRDY BV(3) ///< Master Clock Status
353 #define PMC_SR_OSCSELS BV(7) ///< Slow Clock Oscillator Selection
354 #define PMC_SR_PCKRDY0 BV(8) ///< Programmable Clock Ready Status
355 #define PMC_SR_PCKRDY1 BV(9) ///< Programmable Clock Ready Status
356 #define PMC_SR_PCKRDY2 BV(10) ///< Programmable Clock Ready Status
357 #define PMC_SR_MOSCSELS BV(16) ///< Main Oscillator Selection Status
358 #define PMC_SR_MOSCRCS BV(17) ///< Main On-Chip RC Oscillator Status
359 #define PMC_SR_CFDEV BV(18) ///< Clock Failure Detector Event
360 #define PMC_SR_CFDS BV(19) ///< Clock Failure Detector Status
361 #define PMC_SR_FOS BV(20) ///< Clock Failure Detector Fault Output Status
365 * Defines for bit fields in PMC_IMR register.
368 #define PMC_IMR_MOSCXTS BV(0) ///< Main Crystal Oscillator Status Interrupt Mask
369 #define PMC_IMR_LOCK BV(1) ///< PLL Lock Interrupt Mask
370 #define PMC_IMR_MCKRDY BV(3) ///< Master Clock Ready Interrupt Mask
371 #define PMC_IMR_PCKRDY0 BV(8) ///< Programmable Clock Ready 0 Interrupt Mask
372 #define PMC_IMR_PCKRDY1 BV(9) ///< Programmable Clock Ready 1 Interrupt Mask
373 #define PMC_IMR_PCKRDY2 BV(10) ///< Programmable Clock Ready 2 Interrupt Mask
374 #define PMC_IMR_MOSCSELS BV(16) ///< Main Oscillator Selection Status Interrupt Mask
375 #define PMC_IMR_MOSCRCS BV(17) ///< Main On-Chip RC Status Interrupt Mask
376 #define PMC_IMR_CFDEV BV(18) ///< Clock Failure Detector Event Interrupt Mask
380 * Defines for bit fields in PMC_FSMR register.
383 #define PMC_FSMR_FSTT0 BV(0) ///< Fast Startup Input Enable 0
384 #define PMC_FSMR_FSTT1 BV(1) ///< Fast Startup Input Enable 1
385 #define PMC_FSMR_FSTT2 BV(2) ///< Fast Startup Input Enable 2
386 #define PMC_FSMR_FSTT3 BV(3) ///< Fast Startup Input Enable 3
387 #define PMC_FSMR_FSTT4 BV(4) ///< Fast Startup Input Enable 4
388 #define PMC_FSMR_FSTT5 BV(5) ///< Fast Startup Input Enable 5
389 #define PMC_FSMR_FSTT6 BV(6) ///< Fast Startup Input Enable 6
390 #define PMC_FSMR_FSTT7 BV(7) ///< Fast Startup Input Enable 7
391 #define PMC_FSMR_FSTT8 BV(8) ///< Fast Startup Input Enable 8
392 #define PMC_FSMR_FSTT9 BV(9) ///< Fast Startup Input Enable 9
393 #define PMC_FSMR_FSTT10 BV(10) ///< Fast Startup Input Enable 10
394 #define PMC_FSMR_FSTT11 BV(11) ///< Fast Startup Input Enable 11
395 #define PMC_FSMR_FSTT12 BV(12) ///< Fast Startup Input Enable 12
396 #define PMC_FSMR_FSTT13 BV(13) ///< Fast Startup Input Enable 13
397 #define PMC_FSMR_FSTT14 BV(14) ///< Fast Startup Input Enable 14
398 #define PMC_FSMR_FSTT15 BV(15) ///< Fast Startup Input Enable 15
399 #define PMC_FSMR_RTTAL BV(16) ///< RTT Alarm Enable
400 #define PMC_FSMR_RTCAL BV(17) ///< RTC Alarm Enable
401 #define PMC_FSMR_LPM BV(20) ///< Low Power Mode
405 * Defines for bit fields in PMC_FSPR register.
408 #define PMC_FSPR_FSTP0 BV(0) ///< Fast Startup Input Polarityx
409 #define PMC_FSPR_FSTP1 BV(1) ///< Fast Startup Input Polarityx
410 #define PMC_FSPR_FSTP2 BV(2) ///< Fast Startup Input Polarityx
411 #define PMC_FSPR_FSTP3 BV(3) ///< Fast Startup Input Polarityx
412 #define PMC_FSPR_FSTP4 BV(4) ///< Fast Startup Input Polarityx
413 #define PMC_FSPR_FSTP5 BV(5) ///< Fast Startup Input Polarityx
414 #define PMC_FSPR_FSTP6 BV(6) ///< Fast Startup Input Polarityx
415 #define PMC_FSPR_FSTP7 BV(7) ///< Fast Startup Input Polarityx
416 #define PMC_FSPR_FSTP8 BV(8) ///< Fast Startup Input Polarityx
417 #define PMC_FSPR_FSTP9 BV(9) ///< Fast Startup Input Polarityx
418 #define PMC_FSPR_FSTP10 BV(10) ///< Fast Startup Input Polarityx
419 #define PMC_FSPR_FSTP11 BV(11) ///< Fast Startup Input Polarityx
420 #define PMC_FSPR_FSTP12 BV(12) ///< Fast Startup Input Polarityx
421 #define PMC_FSPR_FSTP13 BV(13) ///< Fast Startup Input Polarityx
422 #define PMC_FSPR_FSTP14 BV(14) ///< Fast Startup Input Polarityx
423 #define PMC_FSPR_FSTP15 BV(15) ///< Fast Startup Input Polarityx
427 * Defines for bit fields in PMC_FOCR register.
430 #define PMC_FOCR_FOCLR BV(0) ///< Fault Output Clear
434 * Defines for bit fields in PMC_WPMR register.
437 #define PMC_WPMR_WPEN BV(0) ///< Write Protect Enable
438 #define PMC_WPMR_WPKEY_S 8
439 #define PMC_WPMR_WPKEY_M (0xffffff << PMC_WPMR_WPKEY_S) ///< Write Protect key mask
440 #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_M & ((value) << PMC_WPMR_WPKEY_S)))
444 * Defines for bit fields in PMC_WPSR register.
447 #define PMC_WPSR_WPVS BV(0) ///< Write Protect Violation Status
448 #define PMC_WPSR_WPVSRC_S 8
449 #define PMC_WPSR_WPVSRC_M (0xffff << PMC_WPSR_WPVSRC_S) ///< Write Protect Violation Source mask
453 * Defines for bit fields in PMC_OCR register.
456 #define PMC_OCR_CAL4_M 0x7f ///< RC Oscillator Calibration bits for 4 MHz mask
457 #define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_M & (value))
458 #define PMC_OCR_SEL4 BV(7) ///< Selection of RC Oscillator Calibration bits for 4 MHz
459 #define PMC_OCR_CAL8_S 8
460 #define PMC_OCR_CAL8_M (0x7f << PMC_OCR_CAL8_S) ///< RC Oscillator Calibration bits for 8 MHz mask
461 #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_M & ((value) << PMC_OCR_CAL8_S)))
462 #define PMC_OCR_SEL8 BV(15) ///< Selection of RC Oscillator Calibration bits for 8 MHz
463 #define PMC_OCR_CAL12_S 16
464 #define PMC_OCR_CAL12_M (0x7f << PMC_OCR_CAL12_S) ///< RC Oscillator Calibration bits for 12 MHz mask
465 #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_M & ((value) << PMC_OCR_CAL12_S)))
466 #define PMC_OCR_SEL12 BV(23) ///< Selection of RC Oscillator Calibration bits for 12 MHz
470 #endif /* SAM3_PMC_H */